Abstract: Ferroelectric (FE) FETs are complex devices where operation relies on both charge trapping and polarization switching. The nonlinear nature of the circuit elements complicates internal device analysis. We use positive-up-negative down (PUND) measurements and developed an algorithm (Direct internal variable extraction, DIVE) to comprehensively quantify internal circuit metrics during FEFET operation. These techniques enabled quantitative root cause studies of defect evolution throughout all phases of a Si FEFET leading to MW closure. Starting with the first write pulse, an excessive SiO2 IL field is revealed that creates defect levels Dit in excess of 1015 cm-2 eV-1 at the HZO-SiO2 interface screening FE polarization while enabling FE switching. Under subsequent early bipolar stress cycling (up to 104 cycles), defect creation commences at the SiO2-Si interface due to high injected hole fluence (0.17 C/m2) during each stress pulse (negative bias instability, NBI) shifting VT,ERS by -0.3 V with accrual of permanently captured charge Nit of up to +5x10-3 C/m2 (3x1012 cm-2). Subsequently, Nit NBI generation at the SiO2-Si accelerates reaching levels of +7x10-2 C/m2 locking both FEFET PRG and ERS ID-VGS characteristics in the FET on-state inducing memory window closure at 105 cycles while FE switching (Psw = 0.34 C/m2) remains essentially intact. These findings guided the down-selection towards suitable semiconductor/FE systems for charge balanced, reliable and high endurance FEFETs.

Bio: Matthias Passlack received his PhD from the Technische Universität Dresden (Germany). He worked in technical and management roles in advanced semiconductor research for AT&T Bell Labs (Murray Hill, NJ), Motorola (Tempe, AZ), Freescale (Tempe, AZ), TSMC (Leuven, Belgium), and is presently a member of TSMC’s San Jose (CA) Corporate Research team. He contributed to diverse semiconductor technologies and is best known for his contributions to MOSFET gate stack development, related analytical techniques, and device physics. He authored and co-authored over 150 publications and more than 70 US patents. He is an IEEE Fellow.