Abstract: Improvements in main memory storage density are primarily driven by technology node scaling, which causes DRAM cell size and cell-to-cell distance to reduce significantly. Unfortunately, technology scaling negatively impacts the reliability of DRAM chips by exacerbating DRAM read disturbance, i.e., accessing a row of DRAM cells can cause bitflips in data stored in other physically nearby DRAM rows. DRAM read disturbance 1) can be reliably exploited to break memory isolation, a fundamental principle of security and privacy in memory subsystems, and 2) existing defenses against DRAM read disturbance are either ineffective or prohibitively expensive. Therefore, it is critical to 1) understand the read disturbance vulnerability of modern DRAM chips and 2) mitigate DRAM read disturbance efficiently and scalably to ensure robust (reliable, secure, and safe) execution in future DRAM-based systems.

This talk summarizes two sets of works.
First, we build a detailed understanding of DRAM read disturbance by rigorously characterizing the read disturbance vulnerability of off-the-shelf modern DRAM chips under varying properties of 1) temperature, 2) memory access patterns, 3) spatial features of victim DRAM cells, and 4) voltage. Our novel observations demystify the large impact of these four properties on DRAM read disturbance and explain their implications on future DRAM read disturbance-based attacks and solutions.

Second, we propose new memory controller-based mechanisms that mitigate read disturbance bitflips efficiently and scalably by 1) selectively throttling unsafe memory accesses (memory accesses that might cause read disturbance bitflips) without requiring proprietary knowledge of DRAM chip internals, 2) leveraging subarray-level parallelism in off-the-shelf DRAM chips to reduce the performance overhead of the maintenance operations that mitigate DRAM read disturbance, and 3) leveraging the spatial variation in read disturbance vulnerability across DRAM cells to reduce the performance overhead of existing read disturbance solutions. Our memory controller-based mechanisms efficiently mitigate DRAM read disturbance and scale well with worsening DRAM read disturbance over DRAM chip generations.

Bio: Giray Yaglikci is currently a researcher in the Safari Research Group in ETH Zürich. He has recently defended his Ph.D. thesis, which focuses on efficiently and scalably mitigating DRAM read disturbance. Giray’s broader research interests span high-performance, energy-efficient, and secure computer architectures. Giray’s research is 1) in part supported by Google Security and Privacy Research Award and Microsoft Swiss Joint Research Center and 2) recognized by the HOST 2024 PhD Dissertation Competition (one of the five finalists), Intel Hardware Security Academic Award in 2022 (one of the four finalists), and ACM PACT 2023 Student Research Competition (the first place).