If you are interested in integrated circuit design and in learning more about the types of experiments conducted at various DoE national laboratories around the country which work on high energy physics (HEP) including various particle accelerators, you should apply to this trainee program. This program will provide you with tuition supplement and a $35k yearly stipend for two academic years of PhD or Master’s program as well as summer training at a DoE national laboratory. It will also introduce you to the HEP design community, the scientific ASIC design challenges they face, and other students across the country who are part of the same program.
This unique and highly selective program recognizes a few top students with expressed interest in Integrated Circuit Design from Stanford, UC Davis, UC Santa Cruz, and University of Texas Arlington.
Expectations of a DoE HEPIC Design trainee include satisfactory progress in the PhD/Master’s program, satisfactory completion of training at a DoE national laboratory for at least one summer, and continued research related to IC design.
*Disbursement of funds will be to the trainee’s institution.
Program Support
Master Students:
- First year
- Winter/Spring tuition supplement
- Stipend for Winter/Spring/ and Summer at National Lab
- Second year
- Fall/Winter tuition supplement
- Spring at National Lab
- Stipend for Fall/Winter/Spring
- Stipends: $3,888 per month ($35,000 per year)
- Supplemental support for university tuition: $20,000 max per year
Ph.D. First-year Students:
- Grant can be combined with departmental support
- For Stanford EE students, this provides 2 years of support.
- Stanford students from other department than EE / students from UC Davis, UC Santa Cruz, and University of Texas Arlington should work with their department/institution for supplemental coverage.
- Grant details:
- Stipend: $35,000 per year for 2 years
- Tuition support: $20,000 per year for 2 years
- Support and placement for work at a National Lab for first summer
Potential Projects
Argonne National Lab
Berkeley Lab
- 28nm Pixel Readout chip
- Ring-Amplifier-Based Analog-to-Digital Converters
- Cryo-Compatible SRAM
- Low-Power, Cryo-Compatible SiPM Readout
- Cryo-Compatible Standard Cells
- Circuit Design in Deep-cryogenic Environment
- Open-Source ASIC Design
Brookhaven National Lab
- Characterization of Radiation Effects in Advanced CMOS Processes
- Cryogenic Frequency Synthesis for Front-End Electronics
- Efficient Readout Methods for Pixelated Radiation Detectors
- Hybrid CMOS-RRAM ML Accelerator for HEP Applications
Fermilab
- Frontend Implementation of AI-Machine Learning Neural Networks for On-Detector Radiation-Hard EDGE Compute
- Cryogenic Data Converters in 22-nm SOI Process for Scaling towards a Million-Qubit Quantum System
- Skipper CCD-in-CMOS Pixelated Readout for EDGE Computing
- Machine Learning on the Edge for Quantum Control feedback loop
- Design of an eFPGA SoC to enable on-sensor edge compute
-
CMOS Modeling and PDK integration for advanced CMOS nodes for Extreme Environment Applications
SLAC
- Design and Characterization of a System-on-Chip ASIC (aka CRYO) for Noble Liquid TPC Experiments
- Readout ASIC on CMOS 28 nm for 4D tracking at future colliders
- Design of circuits in 22 nm FDSOI
- Design of Fast MAPS for Timing Capabilities at Future Colliders
Application Schedule
- Application open: October 3, 2023
- Application deadline: October 31, 2023
- Reference letter deadline: November 5, 2023
- Finalist interviews: early November
- Decisions back: by November 30, 2023
Eligibility
To be eligible to participate in the university-led traineeship program, graduate student candidates must:
- Be a U.S. citizen or a legal permanent resident.
- Be at least 18 years of age.
- Be enrolled full-time in a qualified graduate program at Stanford, UC Davis, UC Santa Cruz, or University of Texas Arlington, either pursuing a Ph.D. (currently 1st year) or a Master’s degree requiring a thesis project in the following fields:
- Physics, with specialization in High Energy Physics or closely related field; or
- Applied or Engineering Physics, with specialization in materials, sensors, and devices; or
- Electrical Engineering, with specialization in ASICs and data acquisition electronics, or
- Systems Engineering, with specialization in complex scientific instrumentation.
- Students who currently hold another industry-sponsored full fellowship will not be considered.
- Students who receive an internship from another company during the traineeship funded years are not eligible.
- Current DOE employees and household members are not eligible.
How to Apply
Candidates must use the online application form and submit:
- Resume or CV, including links to any publications if appropriate.
- Graduate and undergraduate transcripts (unofficial) with GPA.
- One letter of recommendation. Candidates should provide the name and email of reference in the application form. An automatic email with the letter submission instructions will be emailed to the reference. It is the responsibility of the candidate to make sure the letter of recommendation is submitted by their reference by the reference letter deadline.
- Statement of academic and career interests:
- In 500 words or fewer, describe why and how you’re interested in Integrated Circuit Design.
- Include links to any relevant research.
- Include which area(s) and classes of EE interest you most academically and professionally.
- Describe any work you’ve done up to this point that you think is relevant to future work in ICs.
Contacts
UC Davis: Prof. Rajeevan Amirtharajah (ramirtha@ucdavis.edu)
UC Santa Cruz: Prof. Shiva Abbaszadeh (sabbasza@ucsc.edu)
University of Texas Arlington: Prof. Jonathan Asaadi (jonathan.asaadi@uta.edu)
Stanford: Eiko Rutherford (erutherford@stanford.edu) / Prof. Mark Horowitz