Graph computations are challenging for programming and performance due to low data-reuse and irregular data. The UpDown System is co-designed to improve both programmability and performance. In small scale, 1-cycle thread creation and management enables 10-instruction parallel grains, 1-cycle messages enable cheap parallel coordination, and split-transaction DRAM access unlocks massive memory bandwidth, under software control. In large scale, low-diameter networks combined with in-package optics enable radically higher global-bandwidth/package. We’ll share initial UpDown performance studies: 100x vs multicore CPU’s (single-node) and world-beating performance for BFS and Pagerank (scalable). Anecdotal evidence of reduced programming effort will be discussed.

UpDown is being designed as part of the IARPA’s AGILE research program.

Bio: Andrew A Chien is visiting Stanford on sabbatical for 2024-25 AY. At the University of Chicago, he is the William Eckhardt Distinguished Service Professor of Computer Science and Senior Scientist at Argonne National Laboratories. He has led the Zero-carbon Cloud project since 2015, and is known for his research on datacenters, renewable energy and sustainability, cloud resource management and software, large-scale system architecture, and graph computing architecture. Chien is leader of the IARPA funded “UpDown System Project”, designing breakthrough scalable graph analytics systems. Chien has received numerous recognitions for research. Dr. Chien currently serves on the NSF CISE Advisory Committee and DARPA ISAT. He is a Fellow of the ACM, IEEE, and AAAS. He served as EiC of Communications of the ACM, 2017-2022, and Vice President of Research at Intel Corporation from 2005-2010. He served as SAIC Chair Professor of University of California, San Diego and earlier as faculty at the University of Illinois. He received BS, MS, and PhD degrees from the Massachusetts Institute of Technology.