Abstract: Ultra-low energy and area-efficient electronic systems are required to enable untethered computing at the edge of IoT. To realize self-learning edge-AI systems, conventional solely software-driven deep-learning neural networks becomes a major roadblock due the excessive energy expense of training. Hence, fundamental hardware change is likely needed. In this talk, we review our recent material innovations (E.g. Ferroelectric oxides and 2D Material) and we show how close coupling with new micro-architecture innovations (E.g. New memory physical layout and Monolithic 3D IC) may significantly accelerate in-memory computation. We explore wafer-level solution-processed CMOS-compatible use of 2D Material (MoS2/WSe2) to enable high-endurance memristors that can have properties superior to conventional oxide RRAMs. We discuss the use and enabling of multi-gated HZO-based low-thermal-budget ferroelectric oxide memtransistors for new reconfigurable non-volatile logic and interconnect. In co-operation with specific system-level innovations, we review material-system co-design in data encoding for deep convolution neural network. We show through material-device-aware data encoding, error correction, and novel physical memory layout (staggered + Manhattan arrays), that aim to simplify in-memory data processing, one can significantly manage variabilities while accelerating convolution deep neural network operations and offer substantial low-energy opportunities towards reconfigurable Edge-AI systems. Extending similar innovations to photonics, we show that new ferroelectric-lithium niobate integration can enable reconfigurable photonics and in-memory compute for photonics.

Bio: Aaron Thean is the Globalfoundries Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He is also the Deputy President (Academic Affairs) and Provost at NUS. In addition to his administrative duties, he is also the Director of SHINE research center on Next-Generation Hybrid Electronics, where Heterogeneous Integration process and design are investigated to enable new system innovation by chip packaging and other additive processing. Prior to NUS, Aaron Thean was the Vice President of Logic Technologies at IMEC. Working with Semiconductor Industry leaders like Intel, TSMC, Samsung, Globalfoundries, Apple, and Sony, he directed the research and development of next-generation semiconductor technologies and emerging nano-device architectures. Prior to joining IMEC in 2011, he was with Qualcomm’s CDMA technologies in San Diego, California. Aaron and his group worked on Qualcomm’s 20nm and 16nm mobile System-On-Chip technologies. From 2007 to 2009, Aaron was with IBM, where he developed the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors), M.Sc., and Ph.D. degrees in Electrical Engineering (Edmund J. James Scholar). Recognized by Singapore’s National Research Foundation (NRF) to be a NRF Returning Singaporean Scientist, he returned to Singapore to pursue his career as an academic in 2016. He has co-authored over 300 technical papers in the areas of advanced microelectronics and holds more than 50 US patents.