Abstract: Safety-critical designs need to ensure reliable operations even under hostile operating conditions. As these designs grow in size and complexity, they are facing an increased risk of failure. To ensure safety requirements’ compliance, and at the same time to cope with the ever-increasing complexity of modern SoCs, the existing design flows become inadequate as the process is repetitive, time-tedious, and requires high manual efforts.

The model-driven safety verification/analysis flow enables fault injection at different abstraction levels of a design, i.e. fault injection is performed at register transfer level (RTL) of the design, in which parts of the design targeted for fault simulation are represented with gate-level granularity. An automated approach provides statistical model-based fault simulation/emulation solutions independently of the simulator/emulator platform. Formal equivalence check is performed to guarantee the consistency with the initial RTL model and property check is applied to verify the correct behavior of the fault injectors. Moreover, the functional processor verification technique, C-S2-QED, is deployed in the automated flow to provide accurate fault coverage (= pattern independent fault propagation) and functionally verify the hardened designs.

Bio: I earned my Master’s degree at Technical University of Kaiserslautern, Germany in 2020. Currently, I am an industrial PhD candidate at Infineon Technologies AG, Germany and a student at Technical University of Kaiserslautern. My research focuses on model-driven techniques, safety verification and analysis, and recently formal verification.