Energy-Efficient Hardware Systems

Boahen, Dally, Horowitz, Kozyrakis, Mitra, Olukotun

The exponential growth in performance and storage capacity has been the key enabler for information technology for decades. However, the end of voltage scaling in semiconductor chips has made all computer systems, from mobile phones to massive data centers, energy limited. This shift motivates new system architectures and vertical co-design of hardware, system software, and applications. We look at new ways to design, architect, and manage energy-efficient systems for emerging applications ranging from the internet-of-things to big data analytics. Examples include:

  • Hardware design for specialized accelerators and programing models for heterogeneous computing;
  • Scalable parallel architectures with thousands of computing and memory elements;
  • Hardware architectures and systems software for cloud computing;
  • Architectures for new circuits and memory technologies;
  • Reliable and trustworthy architectures.

Faculty

Bill Dally

Bill Dally Professor (Research)

Gates 301 (9045)
Website

George, Sue Administrator

Gates 303 (9045)
725-2340
sue.george@stanford.edu

Mark A. Horowitz

Mark A. Horowitz Professor

Gates 306 (9030)
Website

Swenson, Mary Jane Administrator

Gates 279 (9030)
723-0748
mswenson@cs.stanford.edu

Christos Kozyrakis

Christos Kozyrakis Associate Professor

Gates 304 (9030)
Website

George, Sue Administrator

Gates 303 (9030)
725-2340
sue.george@stanford.edu

Subhasish Mitra

Subhasish Mitra Associate Professor

Gates 336 (9030)
Website

Davis, Beverly Administrator

Clark Center W352 (9030)
723-1458
beverlyd@stanford.edu

Kunle A. Olukotun

Kunle A. Olukotun Professor

Gates 302 (9040)
Website

Hadding, Darlene Administrator

Gates 408 (9040)
723-1430
darleneh@stanford.edu