Undergrad Vivian Wang (BS '17) is a 2017 Churchill Scholarship winner
March 2017

Congratulations to Vivian Wang (BS '17) on her well-deserved award!

As an undergraduate, Vivian has been involved in numerous events on campus. She is a former co-director, and teacher, of Stanford Splash, which brings middle and high school students to campus to learn from Stanford students. Vivian has taught Splash courses since 2014. Her most recent course was "Sewable Electronics."

Vivian has also been a teaching assistant for two of the department's most popular courses, "An Intro to Making: What is EE" and "Digital Systems Design". She was selected through a competitive process, to be a peer tutor in math and physics. Vivian also participated in EE's REU program, doing research, and eventually co-authoring a paper with Professor Jim Harris. Vivian has also worked as an undergraduate research assistant for Professor Amin Arbabian.

"I am grateful for the research and other experiences Stanford has provided me thus far and look forward to the scientific and cultural opportunities provided through the Churchill Scholarship," Wang said.

The goal of the Churchill Scholarships program, established at the request of Sir Winston Churchill, is to advance science and technology on both sides of the Atlantic, helping to ensure future prosperity and security.


Excerpted from Stanford News article, "Stanford electrical engineering senior wins Churchill Scholarship"

March 2017

Kristen Lurie (PhD '16) and Audrey Bowden authored a paper published in Biomedical Optics Express that presents a computational method to reconstruct and visualize a 3D model of organs from an endoscopic video that captures the shape and surface appearance of the organ.

Although the team developed the technique for the bladder, it could be applied to other hollow organs where doctors routinely perform endoscopy, including the stomach or colon.

"We were the first group to achieve complete 3D bladder models using standard clinical equipment, which makes this research ripe for rapid translation to clinical practice," states Kristen Lurie (EE PhD, '16), lead author on the paper.

"The beauty of this project is that we can take data that doctors are already collecting," states Audrey.

One of the technique's advantages is that doctors don't have to buy new hardware or modify their techniques significantly. Through the use of advanced computer vision algorithms, the team reconstructed the shape and internal appearance of a bladder using the video footage from a routine cystoscopy, which would ordinarily have been discarded or not recorded in the first place.

"In endoscopy, we generate a lot of data, but currently they're just tossed away," said Joseph Liao, professor of Urology and co-author. According to Liao, these three-dimensional images could help doctors prepare for surgery. Lesions, tumors and scars in the bladder are hard to find, both initially and during surgery.

This technique is the first of its kind and still has room for improvement, the researchers said. Primarily, the three-dimensional models tend to flatten out bumps on the bladder wall, including tumors. With the model alone, this may make tumors harder to spot. The team is now working to advance the realism, in shape and detail, of the models.

Future directions, according to the researchers, include using the algorithm for disease and cancer monitoring within the bladder over time to detect subtle changes, as well as combining it with other imaging technologies.


Read Paper



Excerpted from Stanford News, "Stanford scientists create three-dimensional bladder reconstruction"


March 2017

Congratulations to Isha Datye and Alexander Gabourie on their winning poster, "Reduction of hysteresis in MoS2 transistors using pulsed voltage measurements". 


The Device Research Conference (DRC) brings together leading scientists, researchers, and students to share their latest discoveries in device science, technology and modeling. 2016 marked the 75th anniversary of the DRC — the longest running device research meeting in the world.



Transistors based on atomically thin two-dimensional (2D) materials like MoS2 have attractive properties for applications in low-power electronics. However, in practice their electrical measurements often exhibit hysteresis, masking their intrinsic behavior. In this study we used pulsed measurements to decrease hysteresis, examine charge trapping, and extract device parameters (like mobility) that represent the "true" behavior of 2D devices. Hysteresis is minimized even with modest ≤ 1 ms pulses, and the extracted mobility converges to a unique value, unlike the less reliable conventional methods which rely either on forward or reverse DC sweeps.

Link to paper

March 2017

Ning Wang, EE PhD candidate, received best paper and best poster awards at TECHCON 2016. The title of his paper is "GDOT: A Graphene-Based Nanofunction for Dot-Product Computation".

TECHCON is a technical conference and networking event for Semiconductor Research Corporation (SRC) members and students.

Ning Wang's research is in Physical Technology & Science and his advisor is Eric Pop.


Congratulations to Ning on his well-deserved recognition!


Though much excitement surrounds two-dimensional (2D) beyond CMOS fabrics like graphene and MoS2, most efforts have focused on individual devices, with few high-level implementations. Here we present the first graphene-based dot-product nanofunction (GDOT) using a mixed-signal architecture. Dot product kernels are essential for emerging image processing and neuromorphic computing applications, where energy efficiency is prioritized. SPICE simulations of GDOT implementing a Gaussian blur show up to ~10(4) greater signal-to-noise ratio (SNR) over CMOS based implementations - a direct result of higher graphene mobility in a circuit tolerant to low on/off ratios. Energy consumption is nearly equivalent, implying the GDOT can operate faster at higher SNR than CMOS counterparts while preserving energy benefits over digital implementations. We implement a prototype 2-input GDOT on a waferscale 4" process, with measured results confirming dot-product operation and lower than expected computation error.


February 2017

In an article titled, "Graphene-Girded Interconnects Could Enable Next-Gen Chips," work by EE PhD candidate Ling Li, a Nanoelectronics Lab researcher, provides insight to the possible future of copper and graphene.

At the IEEE International Electron Devices Meeting in San Francisco in December, researchers described the coming problems for copper interconnects, and debated ways of getting around them. One approach studied by H.-S. Philip Wong's Nanoelectronics Lab, is to bolster copper with graphene. The research group found that the nanomaterial can alleviate a major problem facing copper, called electron migration.

Copper wires are getting so thin, and must carry so much current, that the atoms in the wire can literally get blown out of place. "The electron wind can physically move the copper atoms and create a void," says Wong. Growing graphene around copper wires prevents this, according to research Wong's group presented at the meeting. It also seems to bring down the resistance of the copper wires.

The Stanford group worked with Lam Research, which makes chip manufacturing tools, as well as researchers from Zhejiang University, in China, to make and test the composite interconnects. The materials are a good pair: graphene is often made by growing it on copper. Lam Research has developed a proprietary process for doing this at temperatures that won't damage the rest of the chip—below 400 °C. Compared to copper alone, the composite improved electromigration by a factor of 10. And the composite wires had half the electrical resistance.

Wong says the interconnect problem can no longer be dismissed. "Before, most of the time we were hearing about transistors," he says. "Now it's not just transistors but wires, memory—many other things that were previously not a problem are beginning to be a problem."


Excerpted from IEEE Spectrum, 6 January 2017.

February 2017

Mingyu Gao (PhD '18) and co-authors received the acknowledgement at ISCA 2016. Their paper is titled, "DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric".

IEEE Micro will include a complete list of 2016's significant papers in its annual publication, "Micro's Top Picks from the Computer Architecture Conferences" in its May / June 2017 issue. The issue collects some of the year's most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper (not a combination of papers) published in the top conferences of 2016 (including MICRO-49) is eligible. The Top Picks committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.



FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need.

This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations like bitline precharge and charge restoration with routing within the reconfigurable routing fabric to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators with minimal latency. Overall, DRAF trades off some of the performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by more than 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks, including analytics and interactive services like speech recognition.


Congratulations to Mingyu and co-authors. His research advisor is Christos Kozyrakis

January 2017

 "It's all in the name," state Professors Jonathan Fan and Roger Howe.

"Experimental fabrication. We want to change the way that people go from thinking about a device to making it in the lab. With ExFab, we will make that process faster and cheaper, with fewer restrictions on materials. It will allow the rapid prototyping of microscale and nanoscale devices in a time scale not typically associated with microelectronic fabrication, and it will bring together researchers from in engineering, medicine, and the basic sciences.

"With our investment in the tools and space, we can explore how it's used, and let that guide us in how to develop the space into the future."

ExFab emerged from a two-year process of faculty brainstorming about how best to address the need for new tools and processes for research in materials, electronics, and photonics. In addition, faculty also wanted to study how the new tools and space are used. The goal was to create an accessible space for faster, cheaper fabrication of a wider range of materials and processes.

Strategically located in the Allen Building near the engineering quad and the David Packard building, and across from the Medical School, ExFab is open to all: Stanford students and postdocs from all departments and schools, as well as researchers from other universities and industry.

Repurposing existing space, ExFab boasts several new tools, including those that can translate computer-generated images into physical microscale and nanoscale patterns within minutes. Many of these tools are housed in a reconfigured cleanroom. Complementing the System Prototyping Facility (SPF) – just a few steps away – students can easily utilize both areas to integrate fabricated devices into electronic systems.

In Spring, ExFab will be fully outfitted with equipment enabling researchers to define structures from the nanoscale (two-photon 3D printing) to the milli-scale (3D wax printing) and in between (direct-write lithography, aerosol jet printing) as well as to machine and meld disparate materials (laser cutting, CNC micromilling, grinding, bonding.) This toolset supports heterogeneous materials processing for emerging applications such as stretchable electronics, micro-batteries, photovoltaics, and microfluidics. With lower materials restrictions than a typical microelectronics fab, we anticipate the processing of a broad range of materials into devices and systems, including traditional semiconductors, soft materials, polymers, and bio-materials.

Nine months ago, excited for the potential of this proposed lab, over 30 faculty pledged they would use ExFab for their research, thus seeding this program. Now ExFab is a reality, and available to all. If you are an interested researcher or faculty, please email or check out the website, to learn more.


Pictured below (left to right) Jon Fan, Mary Tang, and Roger Howe in a nearly completed ExFab space.

Amin Arbabian
January 2017

The Department of Energy (DOE) announced projects selected as part of the Rhizosphere Observations Optimizing Terrestrial Sequestration (ROOTS) program funding opportunity. ROOTS is a new program of the Energy Department's Advanced Research Projects Agency-Energy (ARPA-E).

Amin Arbabian's project, "Thermoacoustic Root Imaging, Biomass Analysis, and Characterization," has been awarded $2 million by the ROOTS program. The team also includes, (Pierre Khuri-Yakub EE, José Dinneny and David Ehrhardt, Carnegie Institution for Science) and will develop a non-contact, high throughput, thermoacoustic root imaging system where ultrasonic signals from roots are generated by radio signals and then recorded by a novel sensor array. The Stanford team will demonstrate use of the system across a variety of soil and root types in the field to map the root architecture of plants. If successful, the project will be the first low-cost, large-scale, field-based plant phenotyping solution for eventual use with a fully autonomous measurement system.

The Rhizosphere Observations Optimizing Terrestrial Sequestration (ROOTS) program seeks to develop advanced technologies and crop cultivars that enable a 50 percent increase in soil carbon accumulation while reducing N2O emissions by 50 percent and increasing water productivity by 25 percent. Since 2009, ARPA-E has funded over 400 potentially transformational energy technology projects.

ROOTS projects will tackle the growing problem of soil "carbon debt" by developing sensing technologies to help farmers choose crop varieties that better capture carbon molecules from the atmosphere and store them in their root systems.


Arpa-E Roots Program:

ROOTS program project descriptions (PDF) 

November 2016

Sachin Katti and Pengyu Zhang, a postdoctoral researcher in Katti's lab, announced "HitchHike" this week at the ACM SenSys Conference. HitchHike is a tiny, ultra-low-energy wireless radio.

"HitchHike is the first self-sufficient WiFi system that enables data transmission using just micro-watts of energy – almost zero," Zhang said. "Better yet, it can be used as-is with existing WiFi without modification or additional equipment. You can use it right now with a cell phone and your off-the-shelf WiFi router."

HitchHike is so low-power that a small battery could drive it for a decade or more, the researchers say. It even has the potential to harvest energy from existing radio waves and use that electromagnetic energy, plucked from its surroundings, to power itself, perhaps indefinitely.

"HitchHike could lead to widespread adoption in the Internet of Things," Katti said. "Sensors could be deployed anywhere we can put a coin battery that has existing WiFi. The technology could potentially even operate without batteries. That would be a big development in this field."

The researchers say HitchHike could be available to be incorporated into wireless devices in the next three to five years.

The Hitchhike prototype is a processor and radio in one. It measures about the size of a postage stamp, but the engineers believe that they can make it smaller – perhaps even smaller than a grain of rice for use in implanted bio-devices like a wireless heart rate sensor (see video).

"HitchHike opens the doors for widespread deployment of low-power WiFi communication using widely available WiFi infrastructure and, for the first time, truly empower the Internet of Things," Zhang said.



Excerpted from Stanford Engineering News. Original article by Andrew Myers


November 2016

Lab64, a new electrical engineering laboratory and workspace located on the bottom floor of Packard, held its grand opening October 19. The workspace, also known as the Packard makerspace, is open 24 hours, seven days a week for any Stanford students interested in building electronics.

The full space consists of a series of rooms in Packard that have been retooled expressly as a makerspace. Cleaned out and filled with various electronic equipment, the walls are for writing on and brainstorming ideas.

Students of all majors can use the space after they view a short lab safety presentation and email the Lab64 manager. To further promote safety, lab64 has a buddy system that requires students to work in pairs when they use the space.

"Whether you're an electrical engineer or an art major who wants to use lights in your art pieces, we want everyone working here," said lab64 course assistant Sam Girvin '16.

The lab is currently equipped with what Girvin calls "typical lab bench stuff," including oscilloscopes, power supplies, soldering irons and a 3D printer. A laser cutter is also expected to be purchased in the coming weeks.

Lab64 was created because the electrical engineering department has wanted to help create a "maker" culture at the University for years, according to Girvin. Students now have a place to build whenever they have project ideas; they can go beyond building for class assignments.

"When I came to Stanford as a freshman, there wasn't an easy place to make things," Girvin said. "So I'm really excited about this."

During the opening event, students chatted over pizza and cookies and listened to presentations about the space. Attendees were then split into two workshop groups to explore the lab's capabilities: One group built a working AM/FM radio and the other, a functioning game console that plays the game Snake.

"This is a way to get into building important personal projects," said Zach Belateche '20, a prospective electrical engineering major and lab64 visitor. "Whether it's right after class or midnight on a Sunday, I can come here and work on things I care about."

Packard's makerspace has a team of mentors who can guide students to use the equipment effectively and safely. lab64 can be used by anyone, not just electrical engineers.

"We're trying to get as many different people to come in as we can," Girvin said. "We're willing to teach as much as people are willing to learn."

The lab supplies all equipment and basic materials for free, but a "Maker Store" is also set to open soon in Packard. It will sell more specific items that students may need to complete their projects.

Lab64 is not just a place to work with electrical equipment. Ultimately, the goal is to create a community where people can work, chat and talk about projects. 




Excerpted from The Stanford Daily, October 21, 2016. Original article by Max Pienkny


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