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Publication # 275 |
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Jun-Fei
Zheng, Jesper Hanberg, Hilmi Volkan Demir, Vijit A. Sabnis, Onur
Fidaner, James S. Harris, Jr., David A. B. Miller, "Novel
passivation and planarization in the integration of III-V semiconductor
devices," "Optoelectronic Integrated Circuits VIII conference at SPIE's
Integrated Optoelectronic Devices 2004 symposium 25-29 Jan. 2004, San
Jose, CA, USA (Photonic West 2004). Proc. SPIE Vol. 5356, p. 81-91,
Optoelectronic Integrated Circuits VI; Louay A. Eldada; Ed., Jun 2004 III-V semiconductor devices typically use structures grown layer-by-layer and require passivation of sidewalls from vertical etching to reduce leakage. The passivation is conventionally achieved by sealing the sidewalls using polymer and the polymer needs to be planarized by polymer etch-back method to the level of device top for metal interconnection. It is very challenging to achieve perfect planarization needed for sidewalls of all the device layers including the top layer to be completely sealed. We introduce a novel hard-mask-assisted self-aligned planarization process that allows the polymer in 1-3 µm vicinity of the devices to be planarized perfectly with the device top. The hard-mask-assisted process also allows self-aligned via formation for metal interconnect to device top of µm size. The hard mask is removed to expose a very clean device top surface for low ohmic contact resistance before device top metalization. The process is robust because it is insensitive to device height difference, spin-on polymer thickness variation, and polymer etch non-uniformity. We have demonstrated high yield fabrication of monolithically integrated optical switch arrays with mesa diodes and waveguide electroabsorption modulator on InP substrate with yield > 90%, high breakdown voltage of > 10 Volts, and low ohmic contact resistance of 10-20 Ω |
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