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February 2017

In an article titled, "Graphene-Girded Interconnects Could Enable Next-Gen Chips," work by EE PhD candidate Ling Li, a Nanoelectronics Lab researcher, provides insight to the possible future of copper and graphene.

At the IEEE International Electron Devices Meeting in San Francisco in December, researchers described the coming problems for copper interconnects, and debated ways of getting around them. One approach studied by H.-S. Philip Wong's Nanoelectronics Lab, is to bolster copper with graphene. The research group found that the nanomaterial can alleviate a major problem facing copper, called electron migration.

Copper wires are getting so thin, and must carry so much current, that the atoms in the wire can literally get blown out of place. "The electron wind can physically move the copper atoms and create a void," says Wong. Growing graphene around copper wires prevents this, according to research Wong's group presented at the meeting. It also seems to bring down the resistance of the copper wires.

The Stanford group worked with Lam Research, which makes chip manufacturing tools, as well as researchers from Zhejiang University, in China, to make and test the composite interconnects. The materials are a good pair: graphene is often made by growing it on copper. Lam Research has developed a proprietary process for doing this at temperatures that won't damage the rest of the chip—below 400 °C. Compared to copper alone, the composite improved electromigration by a factor of 10. And the composite wires had half the electrical resistance.

Wong says the interconnect problem can no longer be dismissed. "Before, most of the time we were hearing about transistors," he says. "Now it's not just transistors but wires, memory—many other things that were previously not a problem are beginning to be a problem."

 

Excerpted from IEEE Spectrum, 6 January 2017.

February 2017

Mingyu Gao (PhD '18) and co-authors received the acknowledgement at ISCA 2016. Their paper is titled, "DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric".

IEEE Micro will include a complete list of 2016's significant papers in its annual publication, "Micro's Top Picks from the Computer Architecture Conferences" in its May / June 2017 issue. The issue collects some of the year's most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper (not a combination of papers) published in the top conferences of 2016 (including MICRO-49) is eligible. The Top Picks committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

 


 

Abstract:
FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need.

This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations like bitline precharge and charge restoration with routing within the reconfigurable routing fabric to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators with minimal latency. Overall, DRAF trades off some of the performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by more than 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks, including analytics and interactive services like speech recognition.

 

Congratulations to Mingyu and co-authors. His research advisor is Christos Kozyrakis

January 2017

 "It's all in the name," state Professors Jonathan Fan and Roger Howe.

"Experimental fabrication. We want to change the way that people go from thinking about a device to making it in the lab. With ExFab, we will make that process faster and cheaper, with fewer restrictions on materials. It will allow the rapid prototyping of microscale and nanoscale devices in a time scale not typically associated with microelectronic fabrication, and it will bring together researchers from in engineering, medicine, and the basic sciences.

"With our investment in the tools and space, we can explore how it's used, and let that guide us in how to develop the space into the future."

ExFab emerged from a two-year process of faculty brainstorming about how best to address the need for new tools and processes for research in materials, electronics, and photonics. In addition, faculty also wanted to study how the new tools and space are used. The goal was to create an accessible space for faster, cheaper fabrication of a wider range of materials and processes.

Strategically located in the Allen Building near the engineering quad and the David Packard building, and across from the Medical School, ExFab is open to all: Stanford students and postdocs from all departments and schools, as well as researchers from other universities and industry.

Repurposing existing space, ExFab boasts several new tools, including those that can translate computer-generated images into physical microscale and nanoscale patterns within minutes. Many of these tools are housed in a reconfigured cleanroom. Complementing the System Prototyping Facility (SPF) – just a few steps away – students can easily utilize both areas to integrate fabricated devices into electronic systems.

In Spring, ExFab will be fully outfitted with equipment enabling researchers to define structures from the nanoscale (two-photon 3D printing) to the milli-scale (3D wax printing) and in between (direct-write lithography, aerosol jet printing) as well as to machine and meld disparate materials (laser cutting, CNC micromilling, grinding, bonding.) This toolset supports heterogeneous materials processing for emerging applications such as stretchable electronics, micro-batteries, photovoltaics, and microfluidics. With lower materials restrictions than a typical microelectronics fab, we anticipate the processing of a broad range of materials into devices and systems, including traditional semiconductors, soft materials, polymers, and bio-materials.

Nine months ago, excited for the potential of this proposed lab, over 30 faculty pledged they would use ExFab for their research, thus seeding this program. Now ExFab is a reality, and available to all. If you are an interested researcher or faculty, please email snf-access@stanford.edu or check out the website, snf.stanford.edu to learn more.

 

Pictured below (left to right) Jon Fan, Mary Tang, and Roger Howe in a nearly completed ExFab space.

Amin Arbabian
January 2017

The Department of Energy (DOE) announced projects selected as part of the Rhizosphere Observations Optimizing Terrestrial Sequestration (ROOTS) program funding opportunity. ROOTS is a new program of the Energy Department's Advanced Research Projects Agency-Energy (ARPA-E).

Amin Arbabian's project, "Thermoacoustic Root Imaging, Biomass Analysis, and Characterization," has been awarded $2 million by the ROOTS program. The team also includes, (Pierre Khuri-Yakub EE, José Dinneny and David Ehrhardt, Carnegie Institution for Science) and will develop a non-contact, high throughput, thermoacoustic root imaging system where ultrasonic signals from roots are generated by radio signals and then recorded by a novel sensor array. The Stanford team will demonstrate use of the system across a variety of soil and root types in the field to map the root architecture of plants. If successful, the project will be the first low-cost, large-scale, field-based plant phenotyping solution for eventual use with a fully autonomous measurement system.

The Rhizosphere Observations Optimizing Terrestrial Sequestration (ROOTS) program seeks to develop advanced technologies and crop cultivars that enable a 50 percent increase in soil carbon accumulation while reducing N2O emissions by 50 percent and increasing water productivity by 25 percent. Since 2009, ARPA-E has funded over 400 potentially transformational energy technology projects.

ROOTS projects will tackle the growing problem of soil "carbon debt" by developing sensing technologies to help farmers choose crop varieties that better capture carbon molecules from the atmosphere and store them in their root systems.

 

Arpa-E Roots Program: https://arpa-e.energy.gov/?q=arpa-e-programs/roots

ROOTS program project descriptions (PDF) 

November 2016

Sachin Katti and Pengyu Zhang, a postdoctoral researcher in Katti's lab, announced "HitchHike" this week at the ACM SenSys Conference. HitchHike is a tiny, ultra-low-energy wireless radio.

"HitchHike is the first self-sufficient WiFi system that enables data transmission using just micro-watts of energy – almost zero," Zhang said. "Better yet, it can be used as-is with existing WiFi without modification or additional equipment. You can use it right now with a cell phone and your off-the-shelf WiFi router."

HitchHike is so low-power that a small battery could drive it for a decade or more, the researchers say. It even has the potential to harvest energy from existing radio waves and use that electromagnetic energy, plucked from its surroundings, to power itself, perhaps indefinitely.

"HitchHike could lead to widespread adoption in the Internet of Things," Katti said. "Sensors could be deployed anywhere we can put a coin battery that has existing WiFi. The technology could potentially even operate without batteries. That would be a big development in this field."

The researchers say HitchHike could be available to be incorporated into wireless devices in the next three to five years.

The Hitchhike prototype is a processor and radio in one. It measures about the size of a postage stamp, but the engineers believe that they can make it smaller – perhaps even smaller than a grain of rice for use in implanted bio-devices like a wireless heart rate sensor (see video).

"HitchHike opens the doors for widespread deployment of low-power WiFi communication using widely available WiFi infrastructure and, for the first time, truly empower the Internet of Things," Zhang said.

 

 

Excerpted from Stanford Engineering News. Original article by Andrew Myers

 

November 2016

Lab64, a new electrical engineering laboratory and workspace located on the bottom floor of Packard, held its grand opening October 19. The workspace, also known as the Packard makerspace, is open 24 hours, seven days a week for any Stanford students interested in building electronics.

The full space consists of a series of rooms in Packard that have been retooled expressly as a makerspace. Cleaned out and filled with various electronic equipment, the walls are for writing on and brainstorming ideas.

Students of all majors can use the space after they view a short lab safety presentation and email the Lab64 manager. To further promote safety, lab64 has a buddy system that requires students to work in pairs when they use the space.

"Whether you're an electrical engineer or an art major who wants to use lights in your art pieces, we want everyone working here," said lab64 course assistant Sam Girvin '16.

The lab is currently equipped with what Girvin calls "typical lab bench stuff," including oscilloscopes, power supplies, soldering irons and a 3D printer. A laser cutter is also expected to be purchased in the coming weeks.

Lab64 was created because the electrical engineering department has wanted to help create a "maker" culture at the University for years, according to Girvin. Students now have a place to build whenever they have project ideas; they can go beyond building for class assignments.

"When I came to Stanford as a freshman, there wasn't an easy place to make things," Girvin said. "So I'm really excited about this."

During the opening event, students chatted over pizza and cookies and listened to presentations about the space. Attendees were then split into two workshop groups to explore the lab's capabilities: One group built a working AM/FM radio and the other, a functioning game console that plays the game Snake.

"This is a way to get into building important personal projects," said Zach Belateche '20, a prospective electrical engineering major and lab64 visitor. "Whether it's right after class or midnight on a Sunday, I can come here and work on things I care about."

Packard's makerspace has a team of mentors who can guide students to use the equipment effectively and safely. lab64 can be used by anyone, not just electrical engineers.

"We're trying to get as many different people to come in as we can," Girvin said. "We're willing to teach as much as people are willing to learn."

The lab supplies all equipment and basic materials for free, but a "Maker Store" is also set to open soon in Packard. It will sell more specific items that students may need to complete their projects.

Lab64 is not just a place to work with electrical equipment. Ultimately, the goal is to create a community where people can work, chat and talk about projects. 

 

 

 

Excerpted from The Stanford Daily, "Makerspace opens, available for students to build," October 21, 2016.

November 2016


Yanjun Han (PhD candidate) and co-authors Jiantao Jiao (PhD candidate) and Professor Tsachy Weissman received the ISITA 2016 Student Paper Award. The award was announced at the International Symposium on Information Theory and its Applications (ISITA2016) event in Monterey, California.

Their paper is titled, "Minimax Rate-Optimal Estimation of KL Divergence between Discrete Distributions."

Congratulations to Yanjun, Jiantao and Tsachy!

 

 

October 2016

Congratulations to David H. Lin (PhD '16), Eshan Singh (PhD candidate), and Professor Subhasish Mitra for receiving the 2015 IEEE International Test Conference (ITC) Best Paper Award.

To encourage excellence in its technical program, ITC presents awards to authors of outstanding papers presented at ITC and published in the proceedings. In determining award-winning papers, the ITC Awards Selection Committee considers the quality of the papers as published in the Proceedings and as presented at the conference technical sessions. The committee's decisions are based on responses by conference attendees as recorded on session rating cards and on the observations and recommendations of the ITC Program Committee.

Their paper, "A Structured Approach to Post-Silicon Validation and Debug using Symbolic Quick Error Detection", has been selected as the Best Paper for International Test Conference (ITC).

The Best Paper Award will be presented to Mitra and co-authors during the plenary session at ITC on November 15th.

 

Congratulations to all!

October 2016

 

A dozen teams of EE students came together Friday afternoon to compete in EE's Annual Pumpkin Carving Contest.

This year's event was hosted in the Packard Atrium, with plenty of candy, refreshments, and music. Judges included student services staff Meo Kittiwanich and Teresa Nguyen, graduate advisor Kai Zang, and Professor Mary Wootters. Judging criteria included completeness, technical skill, creativity, and costumes.

The timed competition resulted in a variety of creative and clever pumpkins, from classic carved and painted pumpkins to IoT trick-or-treater sensing pumpkins that send texts to alert their presence at the door.

  • Third Place went to the "PBBB&J" team of Nicole Grimwood, Nicolo Maganzini, Sophia Williams, and Tong Mu.
  • Second place went to "Pumpkin-Bombking" Team, whose members are Anqi Ji, Elias, Wang, Stanislav Fort, and Philip Lee.
  • The First place team was "2ndPlace4ever," Chris Vassos, Stephania Hsu, Lisa Yamada, and Abubakar Abid.

 

Happy HallowEEn!

Prof. Sachin Katti (pictured left) and Dinesh Bharadia (pictured right) at EE commencement 2016
October 2016

The Marconi Society honors Dinesh Bharadia (PhD '16) with the 2016 Paul Baran Young Scholar Award. Dedicated to furthering scientific achievements in communications and the internet, the Marconi Society will honor four scholars for their outstanding research and innovations in networking. The 2016 Paul Baran Young Scholars Awards will be presented at a gala on November 2 at the Computer History Museum in Mountain View, CA.

"Bharadia's research disproved a long-held assumption that, it is generally not possible for a radio to receive and transmit on the same frequency band because of the interference that results," reads the announcement.

The self-interference cancellation filter Bharadia developed also unleashed the potential for many more applications. The unique architecture had to allow cancellation in all environments. According to Bharadia's PhD advisor, Sachin Katti, "Dinesh's work enables a whole host of new applications, from extremely low-power Internet of Things connectivity to motion tracking. It has the potential to be used for important future applications such as building novel wireless imaging that can enable accuracy in driverless cars during severe weather scenarios, helping blind people to navigate indoors, and much more."

Bharadia thinks receiving the Marconi Young Scholar award is especially rewarding because his work has a direct connection to Marconi. "Marconi invented the radio and I was able to make radios full-duplex," he says. "It's fitting that this work should be recognized by the Marconi Society."

 

Hearty congratulations to Dinesh Bharadia!

 

Excerts from the Marconi Society press release.

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