Nanoelectronics Lab research cited in IEEE Spectrum

February 2017

In an article titled, "Graphene-Girded Interconnects Could Enable Next-Gen Chips," work by EE PhD candidate Ling Li, a Nanoelectronics Lab researcher, provides insight to the possible future of copper and graphene.

At the IEEE International Electron Devices Meeting in San Francisco in December, researchers described the coming problems for copper interconnects, and debated ways of getting around them. One approach studied by H.-S. Philip Wong's Nanoelectronics Lab, is to bolster copper with graphene. The research group found that the nanomaterial can alleviate a major problem facing copper, called electron migration.

Copper wires are getting so thin, and must carry so much current, that the atoms in the wire can literally get blown out of place. "The electron wind can physically move the copper atoms and create a void," says Wong. Growing graphene around copper wires prevents this, according to research Wong's group presented at the meeting. It also seems to bring down the resistance of the copper wires.

The Stanford group worked with Lam Research, which makes chip manufacturing tools, as well as researchers from Zhejiang University, in China, to make and test the composite interconnects. The materials are a good pair: graphene is often made by growing it on copper. Lam Research has developed a proprietary process for doing this at temperatures that won't damage the rest of the chip—below 400 °C. Compared to copper alone, the composite improved electromigration by a factor of 10. And the composite wires had half the electrical resistance.

Wong says the interconnect problem can no longer be dismissed. "Before, most of the time we were hearing about transistors," he says. "Now it's not just transistors but wires, memory—many other things that were previously not a problem are beginning to be a problem."

 

Excerpted from IEEE Spectrum, 6 January 2017.