SystemX

Massively parallel, intracellular recording of a large number of neurons across a network is a great technological pursuit in neurobiology, but it has not been achieved. The intracellular recording by the patch clamp electrode boasts unparalleled sensitivity that can measure down to sub-threshold synaptic events, but it is too bulky to be implemented into a dense massive-scale array: so far only ~10 parallel patch recordings have been possible. Optical methods––e.g., voltage-sensitive dyes/proteins––have been developed in hopes of parallelizing intracellular recording, but they have not been able to perform recording from more than ~30 neurons in parallel. As an opposite example, the microelectrode array can record from many more neurons, but this extracellular technique has too low a sensitivity to tap into synaptic activities. In this talk, I would like to share our on-going effort, a silicon chip that conducts intracellular recording from thousands of connected mammalian neurons in vitro, and discuss applications in high-throughput screening, functional connectome mapping, neuromorphic engineering, and data science.

Deep Neural Networks (DNNs) are very large artificial neural networks trained using very large datasets, typically using the supervised learning technique known as backpropagation. Currently, CPUs and GPUs are used for these computations. Over the next few years, we can expect special-purpose hardware accelerators based on conventional digital-design techniques to optimize the GPU framework for these DNN computations. Here there are opportunities to increase speed and reduce power for two distinct but related tasks: training and forward-inference. During training, the weights of a DNN are adjusted to improve network performance through repeated exposure to the labelled data-examples of a large dataset. Often this involves a distributed network of chips working together in the cloud. During forward-inference, already trained networks are used to analyze new data-examples, sometimes in a latency-constrained cloud environment and sometimes in a power-constrained environment (sensors, mobile phones, "edge-of-network" devices, etc.)

Even after the improved computational performance and efficiency that is expected from these special-purpose digital accelerators, there would still be an opportunity for even higher performance and even better energy-efficiency from neuromorphic computation based on analog memories.

In this presentation, I discuss the origin of this opportunity as well as the challenges inherent in delivering on it, with some focus on materials and devices for analog volatile and non-volatile memory. I review our group's work towards neuromorphic chips for the hardware acceleration of training and inference of Fully-Connected DNNs [1-5]. Our group uses arrays of emerging non-volatile memories (NVM), such as Phase Change Memory, to implement the synaptic weights connecting layers of neurons. I will discuss the impact of real device characteristics – such as non-linearity, variability, asymmetry, and stochasticity – on performance, and describe how these effects determine the desired specifications for the analog resistive memories needed for this application. I present some novel solutions to finesse some of these issues in the near-term, and describe some challenges in designing and implementing the CMOS circuitry around the NVM array. I will end with an outlook on the prospects for analog memory-based DNN hardware accelerators.

[1] G. W. Burr et al., IEDM Tech. Digest, 29.5 (2014).
[2] G. W. Burr et al., IEEE Trans. Elec. Dev, 62(11), pp. 3498 (2015).
[3] G. W. Burr et al., IEDM Tech. Digest, 4.4 (2015).
[4] P. Narayanan et al., IBM J. Res. Dev., 61(4/5), 11:1-11 (2017).
[5] S. Ambrogio et al., Nature, to appear (2018).

Millions of people worldwide suffer from neurological disease and injury leading to paralysis, which is often so severe that people are unable to feed themselves or communicate. Cortically-controlled brain-machine interfaces (BMIs) aim to restore some of this lost function by converting neural activity from the brain into control signals for prosthetic devices. I will describe some of our group's recent investigations into basic motor neurophysiology focused on understanding neural population dynamics, pre-clinical BMIs focused on high-performance control algorithm design, and translational BMI development and pilot clinical trial results focused on helping establish clinical viability.

The deployment of artificial intelligence (AI), particularly of systems that learn from data and experience, is rapidly expanding in our society. Verified artificial intelligence (AI) is the goal of designing AI-based systems that have strong, verified assurances of correctness with respect to mathematically-specified requirements. In this talk, I will consider Verified AI from a formal methods perspective. I will describe five challenges for achieving Verified AI, and five corresponding principles for addressing these challenges. I will illustrate these challenges and principles with examples and sample results from the domain of intelligent cyber-physical systems, with a particular focus on autonomous vehicles.

TBA

In this talk I will discuss my work on self-driving vehicles, with an emphasis on accounting for interactions with external counterparts at both the vehicle- and system-levels. Specifically, I will first discuss a decision-making framework that enables a self-driving vehicle to proactively interact with humans to infer their intents, and to use such information for safe and efficient driving. I will then turn the discussion to the operational and economic aspects of autonomous mobility-on-demand (AMoD) systems, with an emphasis on the interaction between AMoD and the electric power network.

Power electronics can be found in everything from cellphones and laptops to gasoline/electric vehicles, industrial motors and inverters that connect solar panels to the electric grid. With close to 80% of electrical energy consumption in the US expected to flow through a power converter by 2030, innovative solutions are required to tackle key issues related to conversion efficiency, power density and cost. This talk will look at the trends in power electronics across different application spaces, describe the ongoing research efforts and highlight the challenges ahead.

Immersive visual and experiential computing systems, i.e. virtual and augmented reality (VR/AR), are entering the consumer market and have the potential to profoundly impact our society. Applications of these systems range from communication, entertainment, education, collaborative work, simulation and training to telesurgery, phobia treatment, and basic vision research. In every immersive experience, the primary interface between the user and the digital world is the near-eye display. Thus, developing near-eye display systems that provide a high-quality user experience is of the utmost importance. Many characteristics of near-eye displays that define the quality of an experience, such as resolution, refresh rate, contrast, and field of view, have been significantly improved over the last years. However, a significant source of visual discomfort prevails: the vergence-accommodation conflict (VAC). Further, natural focus cues are not supported by any existing near-eye display. In this talk, we discuss frontiers of engineering next-generation opto-computational near-eye display systems to increase visual comfort and provide realistic and effective visual experiences.

Neuromorphic computing has recently emerged as one of the most promising option to reduce power consumption of big data analysis, paving the way for artificial intelligence systems with power efficiencies like the human brain. The key device for neuromorphic computing system is given by artificial two-terminal synapses controlling signal processing and transmission. Their conductivity must be changed in an analog/continuous way depending on neural signal strengths. In addition, synaptic devices must have: symmetric/linear conductivity potentiation and depression; a high number of levels (~32), which depend on applications and algorithm performances; high data retention (>10 years) and cycling (>109); ultra-low power consumption (<10fJ); low variability; high scalability (<10nm) and possibility of 3D integration.

A variety of different device technologies have been explored such as phase change memories, ferroelectric random-access memory and resistive random-access memory (RRAM). In each case matching the desired specs is a complex multivariable problem requiring a deep quantitative understanding of the link between material properties at the atomic scale and electrical device performance. We have used a multiscale modeling platform GINESTRATM to illustrate this for the case of RRAM and Ferroelectric tunnel junctions (FTJ).

In the case of RRAM, modeling of key mechanisms shows that a dielectric stack composed of two appropriately chosen dielectrics provides the best solution, in agreement with experimental data. In the case of FTJ, the hysteretic ferroelectric behavior of dielectric stacks fabricated from the orthorhombic phase of doped HfO2 is nicely captured by the simulations. These show that Fe-HfO2 stack can be easily used for analog switching by simply tuning set/reset voltage amplitudes. An added advantage of the simulations is that they point out ways to improve the performance, variability and endurance of the devices in order to meet industrial requirements.

Join SystemX laliance for their SPRING Workshop Week: Apr 30-May 3, 2018. 
Details available on SystemX SPRING workshop page.

SystemX Alliance research broadly encompasses ubiquitous sensing, computing, and communications in various application areas. Currently affiliated SystemX faculty are found in departments across Stanford's School of Engineering and in some areas of natural Sciences and Medicine. Their research agenda is continually evolving in accordance with the interests of Stanford faculty and industry affiliates.