SystemX

SystemX Seminar: Coherent Ising machines for combinatorial optimization - Optical neural networks operating at the quantum limit

Topic: 
Coherent Ising machines for combinatorial optimization - Optical neural networks operating at the quantum limit
Abstract / Description: 

Optimization problems with discrete and continuous variables are ubiquitous in numerous important areas, including operations and scheduling, drug discovery, wireless communications, finance, integrated circuit design, compressed sensing and machine learning. Despite rapid advances in both algorithm and digital computing technology, even modest sized optimization problems that arise in practice may be very difficult to solve on modern digital computers. One alternative of current interest is the adiabatic quantum computing (AQC) or quantum annealing (QA). Sophisticated AQC/QA devices are already under development, but providing dense connectivity between qubits remains a major challenge with serious implications for the efficiency of AQC/QA approaches. In this talk, we will introduce a novel computing system, coherent Ising machine, and describe its theoretical and experimental performance. We start with the physics of quantum-to-classical crossover as a computational mechanism and how to construct such physical devices as quantum neurons and synapses. We show the performance comparison against various classical neural network models implemented in CPU and supercomputers as algorithms. We end the talk by introducing the portal of the QNNCloud service system based on the coherent Ising machines.

Date and Time: 
Monday, January 29, 2018 - 2:00pm
Venue: 
Packard 204

SystemX Seminar: Nanoscale MOSFET Modeling for the Design of Low-power Analog and RF Circuits

Topic: 
Nanoscale MOSFET Modeling for the Design of Low-power Analog and RF Circuits
Abstract / Description: 

The emergence of the Internet of Things (IoT) poses stringent requirements on the energy consumption and has hence become the primary driver for low-power analog and RF circuit design. Implementation of increasingly complex functions under highly constrained power and area budgets, while circumventing the challenges posed by modern device technologies, makes analog and RF circuit design ever more challenging. Some guidance would therefore be invaluable for the designer to navigate the multi-variable design space.

This talk presents low-power analog and RF design techniques that can be applied from device to circuit level. It starts with the presentation of the concept of inversion coefficient IC as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion. Several figures-of-merit (FoM) including the Gm/ID, the Ft and their product Gm ‧ Ft/ID, capturing the various trade-offs encountered in analog and RF circuit design are presented. The simplicity of the IC-based models is emphasized and compared against measurements of 40- and 28-nm bulk CMOS processes and BSIM6 simulations. Finally, a simple technique to extract the basic model parameters from measurements or simulation is described before concluding.

Date and Time: 
Thursday, February 15, 2018 - 4:30pm
Venue: 
Y2E2 111

SystemX Seminar: Advanced SAR ADCs – Efficiency, Accuracy, Calibration and References

Topic: 
Advanced SAR ADCs – Efficiency, Accuracy, Calibration and References
Abstract / Description: 

This talk will discuss several recent techniques that were developed in the context of SAR ADCs. The presentation will show a few design examples with different performance targets. The first topic deals with minimizing power consumption while aiming to increase accuracy by means of linearization and noise reduction techniques. The second topic is about efficient calibration techniques for SAR ADCs. The last part describes a method to co-integrate the reference buffer with the SAR ADC.

Date and Time: 
Friday, February 9, 2018 - 4:00pm
Venue: 
Allen 101X

SystemX Seminar: Using the Stanford Driving Simulator for Human Machine Interaction Studies

Topic: 
Using the Stanford Driving Simulator for Human Machine Interaction Studies
Abstract / Description: 

The driving simulator at Stanford is used for human-in-the-loop, human-machine interaction (HMI) driving studies. Many of the studies focus on shared control between humans and autonomous systems. The simulator’s toolset collects objective driving behavior data directly from the simulator, as well as data streams from eye trackers, cameras and other physiological sensors that we employ to understand human responses to myriad circumstances in the simulated environment.  This presentation will describe the hardware and software associated with the driving studies, what is possible and show some similar labs at other universities. 

Date and Time: 
Thursday, January 25, 2018 - 4:30pm
Venue: 
Y2E2 111

SystemX Seminar: Programmable and Smart Silicon Interposers for 3D Chip Stacks

Topic: 
Programmable and Smart Silicon Interposers for 3D Chip Stacks
Abstract / Description: 

With increased demands for computation and the slowdown of CMOS scaling, alternative methods for further miniaturization of electronics are gaining momentum. Heterogeneous integration (HI) of chips from various manufacturing lines on to a silicon interposer is a newly recognized approach, which has been used in a number of high-performance applications. However, these 3D-IC chip stacks are time-consuming to develop and are application-specific, resulting in prohibitive costs.

Similar cost issues have been addressed in the form of field programmable gate arrays. In an analogous fashion, programmable silicon interposers open new possibilities of design-reuse of silicon for multiple applications, resulting in cost savings and time to market advantages. Programmable re-use of silicon interposers also enables just-in-time manufacturing to simultaneously produce several smaller lots made with high-mix of components.

In addition, programmable silicon interposers for 3D stacking allow system-level control of functions that can be embedded in the interposer, such as power management, built in self-test, and manufacturing defect repair. Power management techniques previously applied to single chip solutions can be re-architected to achieve higher system level efficiency in these 3D chip stack. We will demonstrate one such system built with a smart, programmable silicon interposer from zGlue – the first commercial implementation of a product in this category. This technology will help proliferate internet of things (IoT) devices, give a broader array of choices to product designers, and will accelerate proliferation of electronics in ultra-small form factor for healthcare, industrial as well as consumer space.

Date and Time: 
Thursday, January 18, 2018 - 4:30pm
Venue: 
Y2E2 111

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