Special Seminar: "Pathfinding DTCO: Quantifying Challenges and Opportunities beyond the End of Pitch Scaling"
Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. While the enormous complexity of leading edge technology nodes has been achieved incrementally over time by deliberately limiting each technology node to mostly small evolutionary steps, far more disruptive device and interconnect innovations are necessary to achieve meaningful power-performance-area-cost (PPAC) improvement as we approach the fundamental device-physics and material-science limits of dimensional scaling. The complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing wafer fabrication equipment R&D resources. In this talk we will present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling and to give TEL a leg up in identifying new process challenges and tool innovation opportunities. This presentation will cover the three main components of our pathfinding DTCO flow:
- Standard Cells for DTCO Pathfinding (Lars Liebmann)
- Extraction, Characterization, Circuit Simulation (Daniel Chanemougame)
- Synthesis, Place-and-Route, STCO (Paul Gutwin)