Graduate

Microgrids are a promising and viable solution for integrating the distributed generation resources in future power systems. Similar to large-scale power systems, microgrids are prone to a range of instability mechanisms and are naturally fragile with respect to disturbances. However, existing planning and operation practices employed in large scale transmission grids usually cannot be downscaled to small low-voltage microgrids. This talk will discuss the concept of ad-hoc microgrids that allow for arbitrary interconnection and switching with guaranteed stability. Although the problem of microgrid stability and control has received a lot of attention in the last years, vast majority of existing works assumed that the network configuration is given and fixed. Moreover, only few works have accounted for electromagnetic delays that will be shown to play a critical role in the context of stability.

The talk will introduce a new mathematical framework for characterization and certification of stability in an ad-hoc setting and derive the formal design constraints for both DC and AC networks. In the context of low-voltage DC network, the corresponding derivations will employ the Brayton-Moser potential theory and result in simple conditions on load capacitances that guarantee both small-signal and transient stability. Whereas for AC microgrids, the singular perturbation analysis will be used to derive simple relations for the droop coefficient of neighboring networks. The talk will conclude with a discussion of key open problems and challenges.

Electric distribution systems are transforming from a traditionally passive element to an active component of the Smart Grid with a hitherto unprecedented availability of new technologies, data, control, and options for end-users to participate in the daily operations of the grid. To realize the full potential of this transformation there is a dire need for new architectures, markets, tools, techniques, and testbeds. In that regard, this talk presents a comprehensive approach based on cyber-physical-social system to energy management in the emerging smart distribution system with new research results from on-going efforts. Topics of aggregators, incentive pricing, customer-side intelligence, and sustainability metrics as well as aspects of current and future trends in this research will be addressed.

We are pleased to announce the call for applications for the 2018 Stanford Neurosciences Institute Interdisciplinary Scholar Awards.

These awards provide funding to extraordinary postdoctoral scientists at Stanford University engaging in highly interdisciplinary research in the neurosciences broadly defined.

Selected scholars will be provided funding for two years, to be utilized for payments toward tuition, salary, and health benefits. In addition, our scholars meet for quarterly luncheons, visit each others' labs to learn about different areas of study and research techniques, develop skills to communicate with a non-scientific audience, and present "elevator pitches" of their research aims and accomplishments to the Executive Committee.

• Candidates in a variety of disciplines will be considered: basic and clinical neurosciences, biomedical sciences, physical sciences, social sciences, engineers, and experts in human behavior from the fields of education, law, business, and humanities.
• Women and under-represented minority postdocs are encouraged to apply.
• Applications are due on August 28, 2017 and the awardees will be announced in December 2017.

Dr. Jack Yuan-Chen Sun received BSEE degree from National Taiwan University and MS and Ph.D. from the University of Illinois. He held research and management positions at IBM T.J. Watson Research Center between 1983 and 1997. He joined TSMC R&D in 1997 as Director of Advanced Module Technology, and then Senior Director of Logic Technology. He became Vice President of R&D in 2006, and Chief Technology Officer at TSMC in 2009. He is currently Vice President of Corporate Research and CTO of TSMC.

He made key contributions to the successful energy efficient CMOS logic SOC platforms with highest routed gate density and computation throughput for the foundry/fabless industry at TSMC. He advocated a holistic energy efficient 3Dx3D system scaling concept. Throughout his career, he and his co-workers pioneered and set many world records in CMOS, bipolar, and BiCMOS.

Dr. Sun received a number of technical and management awards from IBM, TSMC, professional societies, and government. He was awarded a TSMC Medal of Honor in 2011. He is an IEEE Fellow for his contributions to CMOS technology. He received the IEEE EDS J.J. Ebers Award recognition in 2015. He has authored and co-authored over 200 papers and conference presentations, 12 US patents, and several ROC patents.

Dr. Carlos H. Diaz received B.S. in EE and Physics and M.S. degree in EE from Universidad de Los Andes, Bogota-Colombia, and Ph.D. degree in EE from University of Illinois at Urbana-Champaign. He is Senior Director of Advanced Technology Research in R&D, Taiwan Semiconductor Manufacturing Company. Prior to joining TSMC in 1998, he was a member of the technical staff at Hewlett-Packard Co.

He has published over 100 journal and conference papers, holds over 30 US patents, and published one book. He served in the IEEE IEDM Technical and Executive Committees and the technical program committees for the IEEE VLSI, SSDM, SISPAD, IRPS, and EOS/ESD international conferences / symposiums. He also served at the International Roadmap for Semiconductors executive committee. Dr. Diaz was elected an IEEE Fellow in 2008 for his contributions to deep-submicron foundry technology. In 2011, he was co-recipient of Annual Innovation Breakthrough Award, Ministry of Economic Affairs, Taiwan R.O.C., conferred to TSMC's 28nm logic technology: Dr. Y.J. Mii and Dr. Burn J. Lin(process integration and process technology leaders), and Dr. Carlos H. Diaz (device engineering leader). He received the 2016 IEEE Andrew Grove Award for sustained contributions to and leadership in foundry advanced CMOS logic technology.

Dog Petting • Music • Arts & Crafts • Gaming • And More!

In addition to the invaluable librarian support and awesome study spots sought after during this time of year, Stanford students are encouraged to drop by the Stanford Libraries just to de-stress.
Students are invited to stop by the many Stanford Libraries to participate in some stress-reducing activities before and during finals. Some of the libraries are hosting special morning coffee and snacks, dog petting dates, and karaoke. Other libraries have decided to designate areas within their buildings for games, puzzles, arts and crafts, and/or are pulling together specially selected novels for those who wish to take a break from studying to read.

The RC64 many-core architecture combines many small cores, many shared memory banks, a hardware scheduler, and two custom active networks-on-chip: cores-to-memories and cores-to-scheduler. A shared-memory, de-synchronized PRAM-like task-based and non-locking programming model promotes simplicity and ease of programming. A theoretical model (almost) justifies increasing the number of cores while making them smaller and slower, maximizing performance-to-power ratio. Several benchmark simulations are demonstrated, showing close to linear speedup and high performance-to-power ratio in signal processing, linear algebra and machine learning applications. A software ecosystem for RC64 is also discussed.

This talk argues for combining the fields of robotic vision and computational imaging. Both consider the joint design of hardware and algorithms, but with dramatically different approaches and results. Roboticists seldom design their own cameras, and computational imaging seldom considers performance in terms of autonomous decision-making.The union of these fields considers whole-system design from optics to decisions. This yields impactful sensors offering greater autonomy and robustness, especially in challenging imaging conditions. Motivating examples are drawn from autonomous ground and underwater robotics, and the talk concludes with recent advances in the design and evaluation of novel cameras for robotics applications.

Full integration of power management circuits has been a vision and a goal of the power electronics and integrated circuits communities for many years, if not decades. However, while exponential semiconductor scaling has had a profound impact on data processing, storage, and communications, the same has not been true for circuits that process and delivery energy. On one hand, this is because power delivery circuits are constrained by the size and efficiency of passive components – inductors and capacitors – and thus by Maxwell's equations and fundamental material properties. Yet, a host of applications, spanning portable computing, IOT, automotive, and renewable energy demand small, lighter, cheaper, and more efficient solutions.

This talk will address some of the current trends relating to advances in active and passive components, as well as new circuit architectures and design paradigms that are positioned to open the pathway to mm-scale in monolithically-integrated power conversion. A particular focus will be on the switched capacitor approach – more specifically on switched capacitor circuits and architectures that can be operated in resonant modes or hybridized with a small inductive impedance. These circuits leverage the fundamental advantages of capacitors compared to inductors, such as much higher energy-density and better scalability. Yet, compared to a pure SC approach, the use of a small amount of magnetic energy storage can dramatically improve power-density, efficiency, and add capabilities for variable regulation.

The talk will present a generalized framework for comparison of arbitrary converter topologies based on a charge-multiplier approach. This will be used to highlight which topologies – some well-known, some yet to be explored – have good prospects for high-density integration. Several past integrated circuit prototypes will be highlighted that achieved records for efficiency and power density in bulk CMOS.

Given a Boolean relational specification G(X, Y), where X and Y are vectors of inputs and outputs respectively, we consider the problem of synthesizing functions F(X) for Y, such that Exists Y. G(X, Y) is semantically equivalent to G(X, F(X)). Such functions are also called Skolem functions for Y in G(X, Y). We focus on the case where G is given as a DAG (Boolean circuit, AIG, ROBDD, etc.), and present a compositional approach that exploits the structure of the DAG to partially solve the problem from (partial) solutions of sub-problems. The compositional step is computationally efficient, can be generalized to arbitrary Boolean operators, and always gives a function F'(X) that is either a Skolem function or an over-approximation of one. While the over-approximation can be refined by SAT-based counterexample guided abstraction refinement (CEGAR) at each step, we argue why it is beneficial to delay the application of CEGAR. We show the effectiveness of the lazy CEGAR approach by experiments on a suite of benchmarks. This talk is based on joint work with S. Akshay. Shetal Shah and Ajith John, and builds on our TACAS 2017 paper.

Cells are highly complex systems that often exhibit multi-physics responses under external stimulus. To achieve holistic cellular characterizations, it is essential to create interfaces that can provide (1) single-cell resolution, (2) multi-modality interfacing with cells, (3) real-time two-way communication (sensing and actuation), (4) compatibility with high throughput massively parallel operations, and (5) possibility of production at commercial quantities. The nanometer-scale complementary metal-oxide semiconductor (CMOS) process is a potential candidate to realize cell-microelectronics interfaces. Electronics-based computations and signal processing, such as machine learning methods, may drastically relax the requirement on the physical interface and lead to further pixel miniaturization.

In this talk, we will present several fully integrated multi-modality CMOS cellular joint sensor/actuator arrays with multiple sensing modalities in every array pixel to characterize different cell physiological responses, including extracellular voltage recording, cellular impedance mapping, optical detection with shadow imaging and bioluminescence sensing, and thermal monitoring. Each pixel also contains electrical voltage/current excitation for cellular stimulation. These reported CMOS cellular joint sensor/actuator arrays is composed up-to 22k multi-modality pixels on each chip with spatial resolution down to 17um*17um/pixel, achieving single-cell resolution. Multi-modality cellular sensing at the pixel level is supported, which enables holistic cell characterization and concurrent joint-modality physiological monitoring on the same cellular sample. Comprehensive biological experiments with different living cell samples demonstrate the functionality.