EE380 Computer Systems Colloquium

EE380 Computer Systems Colloquium presents "Tales from the Risks Forum"

Topic: 
Tales from the Risks Forum
Abstract / Description: 

Peter G. Neumann has moderated the ACM Risks Forum (risks.org) since its inception in 1985. RISKS has reported and discussed a broad spectrum of problems in computer systems, misconceptions, and human failings over the years. In an unusual format for EE380, this session will revisit some of more memorable risks discovered and how they were mitigated. Live attendees will have an opportunity to share unpublished risks they have found, as time permits. (Please limit your proposed contribution to 3 PDF slides.)

Date and Time: 
Wednesday, October 16, 2019 - 4:30pm
Venue: 
Shriram 104

EE380 Computer Systems Colloquium presents "Neural Networks on Chip Design from the User Perspective"

Topic: 
Neural Networks on Chip Design from the User Perspective
Abstract / Description: 

To apply neural networks to different applications, various customized hardware architectures are proposed in the past a few years to boost the energy efficiency of deep learning inference processing. Meanwhile, the possibilities of adopting emerging NVM (Non-Volatile Memory) technology for efficient learning systems, i.e., in-memory-computing, are also attractive for both academia and industry. We will briefly review our past effort on Deep learning Processing Unit (DPU) design on FPGA in Tsinghua and Deephi, and then talk about some features, i.e. interrupt and virtualization, we are trying to introduce into the accelerators from the user's perspective. Furthermore, we will also talk about the challenges for reliability and security issues in NN accelerators on both FPGA and NVM, and some preliminary solutions for now.

Date and Time: 
Wednesday, October 9, 2019 - 4:30pm
Venue: 
Shriram 104

CANCELLED - SPECIAL SEMINAR: Recent Advances in Diagnosis and Error Correcting Codes

Topic: 
CANCELLED -- a future date is being explored --
Abstract / Description: 

Cancelled

This talk has been cancelled because EE380 requires a video of the presentation. The speakers talk includes unpublished ideas and results which can be disclosed to a small group but not to a large group over broadcast video.
Hopefully the talk will be rescheduled next week for a small live audience of specialists. Watch for an announcement if you are interested. 


 

This presentation will highlight some of our recent research results in developing new diagnosis techniques as well as constructing new error correcting codes (ECC) well suited for emerging memory technologies. In particular, a fundamentally new approach for extracting diagnostic information from output response data highly compacted in multiple input signature registers (MISRs) will be described. This approach is based on symbolic canceling and can significantly increase the precision of error location information without requiring any additional hardware or data to be collected. Emerging memory technologies (e.g., phase change memories, spin transfer torque magnetic RAM, etc.) have new error mechanisms and higher error rates than traditional memories. New ECCs with more attractive decoding latency and complexity will be presented for addressing these reliability challenges.

Date and Time: 
Wednesday, October 2, 2019 - 4:00pm
Venue: 
Gates 415

EE380 Computer Systems Colloquium presents MIPS Open

Topic: 
MIPS Open
Abstract / Description: 

During this session, the speakers will provide an overview of Wave Computing's MIPS Open initiative, including details on the program components, how they can be used to design edge SoCs, licensing terms, the design certification process, etc. Mr. Bemanian will also give a demonstration of how to use various program components for real-world example implementations.

Wave Computing released the first MIPS Open program components at the end of March, providing free access to the MIPS RISC architecture without license fees or royalties. The new MIPS Open online environment is live and immediately accessible at www.mipsopen.com. Specific components in the first program release include:

  • MIPS Instruction Set Architecture: A downloadable copy of the latest version of the MIPS 32/64-bit ISA, SIMD, DSP, Multithreading and Virtualization
  • MIPS Open Toolsi: Integrated Development Environment for embedded real-time operating systems and Linux-based systems for embedded products
  • MIPS Open FPGAs: A complete training program including labs, SoC tutorials and sample (non-commercial) RTL code
  • MIPS Open Cores: low power, low footprint microAptiv Microprocessor(MPU) and Microcontroller (MCU) cores targeted for embedded applications

Historical Note The MIPS Architecture and processor was originally developed in the Computer Systems Laboratory at Stanford by a team headed by John Hennessey. MIPS and the UC Berkeley developed SPARC archicture were quintessential RISC architectures: influential, popular, and heavily studied.

Date and Time: 
Wednesday, May 1, 2019 - 4:30pm
Venue: 
Shriram 104

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