EE292L Seminar: Transistor and Logic Design for 5nm Node and Beyond

Transistor and Logic Design for 5nm Node and Beyond
Thursday, April 28, 2016 - 4:30pm
Thornton 102
Victor Moroz, Ph.D. (Synopsys)
Abstract / Description: 

We use rigorous physics-based analysis of transistors scaled to 5nm design rules and beyond, considering several flavors of FinFETs and nanowires with Si and non-Si channels. The transistors are placed into a representative standard library cell for Power-Performance-Area (PPA) analysis. The PPA analysis reveals that Middle-Of-Line (MOL) RC dominates circuit behavior at 5nm design rules. Optimization of the energy-delay trade-off points towards continuing the ongoing fin depopulation trend and possible transition from FinFETs to nanowires. Besides, innovative approaches to building library cells provide simultaneous improvements in energy consumption and in routability of the short library cells. These observations point to the rising role of random variability in determining chip area and cost. We perform comparative analysis of major variability mechanisms and their implications on PPA outcome for different technologies, ranging from 130nm to 2nm design rules.


Victor Moroz grew up as a hunter-gatherer in Siberia, but eventually received Ph.D. degree in Applied Physics from the University of Nizhny Novgorod. Dr. Moroz joined a Stanford spin-off Technology Modeling Associates in 1995, which later became a part of Synopsys, connecting a design company to the manufacturing. Currently Dr. Moroz is an Editor of Electron Device Letters and a Synopsys Scientist, engaged in a variety of projects on analysis of advanced CMOS technology. Several facets of this activity are reflected in 100+ publications and 100+ granted and pending US patents.