As high-performance CPUs shrink into advanced CMOS process technologies, thinning dielectrics and dwindling wire interconnects demand an ever-increasing complexity of reliability analysis, modeling, and design techniques. This is particularly true for CPUs in notebook and desktop computers, in which to maximize the user experience, it is critical to maximize the voltage and frequency for the small fraction of the lifetime when peak performance is actually needed. An overview of methodologies and design considerations for maintaining the silicon reliability of high-performance CPUs is presented, with particular focus on dielectric breakdown and electromigration as the two most critical limiters. As dynamic voltage and frequency scaling has become pervasive in the mobile and embedded processor space, these techniques will become essential to a broader spectrum of the semiconductor industry as their respective frequencies continue to increase.
Tom Burd received his B.S., M.S., and Ph.D. degrees in Electrical Engineering & Computer Science from U.C. Berkeley in 1992, 1994, and 2001, respectively. He joined AMD in 2005, and is currently the physical design architect of a next-generation x86 CPU core. Previously, Dr. Burd has held various technical leadership roles on multiple high-performance x86 microprocessors, including technical leadership for the silicon reliability of several generations of CPU & APU products. Prior to joining AMD, he consulted at several Silicon Valley startups, including Telegent Systems, Raza Microelectronics, and Matrix Semiconductor.