Today, designers of specialized systems are increasingly tantalized by the enormous energy efficiency of custom silicon solutions...but are just as turned off by the spiraling costs of building and verifying those very chips. Enter the FPGA, a reconfigurable substrate that would be the absolutely perfect solution were it not for two common conventional wisdoms: they're impossible to build, and impossible to use. In this talk we will discuss the motivation and context of FPGAs, notably from the perspective of IO circuits, and what interesting problems and solutions they pose to designers and users.
Ron Ho spends his days and nights hanging out with FPGA IO designers. He started his career at Intel from 1993-2003, where he worked on chips from the 486 to Pentium/PentiumII to Itanium3 processors. From 2003-2014 he was at Sun/Oracle where he worked on capacitively and optically coupled IO circuits, 3D-stacked memories, and big-data appliance accelerators. In late 2014 he joined Altera, now the Programmable Solutions Group within Intel (oh hey haven't we been here before?). At Intel, he is currently Sr. Director of Programmable Hardware IO Systems, so he can be blamed for all the circuits that carry bits off of the FPGA to the outside world, either to external memories or networking backplanes and cables. Ron received his Ph.D. in E.E. from Stanford University. He has some 60 U.S. patents and has co-authored some 100 publications, yet has learned that compared to his two pre-teen daughters, he doesn't know anything, geez.