In this talk a 3D-integrated CMOS/Silicon-photonic receiver will be presented. This receiver is designed to effectively take advantage of low-cap silicon photonic photodiodes and advanced 3D-integration technologies. The electronic chip features an integrating receiver based on a low-bandwidth TIA that employs double-sampling and equalization through dynamic offset modulation. This architecture is also implemented in a 4-channel WDM-based parallel optical receiver using a forwarded clock at quarter-rate. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range.
When electronics and photonics are closely integrated they provide a great promise for improving interconnect performance and reduce cost. Holistic design of co-integrated optical interconnects provides a unique opportunity to design entirely new architectures and bring the performance of current systems to unprecedented levels. In this light, I will cover some future directions for my research beyond data communication such as sensors, computing and networking applications.