Internet and mobile application have been driving force for semiconductor innovation in the past 10 years. It's commonly known that memory and energy walls have been limiting the end-user's perceivable performance. We will focus on the system requirement for the consumer device, such as laptop, phone, watch or glass. We'll start with the high-level workloads, such as web browsing, YouTube streaming, Gaming or photo application. Then break it down to full-system architecture simulation, performance and power analysis. Finally, a few future research areas in memory architecture, technology and circuit design will be discussed.
Eric Shiu is currently a SoC (system on chip) architect at Google's consumer hardware group. He received MSEE from Stanford University in 1998. He was a custom circuit and RTL designer at Sun Micro's UltraSPARC group from 1998 to 2004. He was a principal engineer at PA Semi's SOC group responsible for IO memory, L2 cache architecture and foundry technology from 2004 to 2008. He led the circuit methodology team and was the memory sub-system micro-architect in Appe's A-series SOC from 2008 to 2014. He has authored and co-authored 20+ patents in the area of memory circuits and architecture. His passion is to make technology accessible and affordable to the 99%.
Allan Knies is currently the simulation and performance lead in Google's Consumer Hardware group. He received his MS and PhD degrees from Purdue University and BS in Math and CS from Ohio University. Prior to joining Google, he worked at Intel on a wide variety of projects including the development and evaluation of the Itanium instruction set, managing Intel's Berkeley Research lab, and the development of ultra-efficient and scalable computers as part of the DoE FastForward program. He is a member of Phi Beta Kappa and Eta Kappa Nu.