Special Seminar

Technology for the 6th decade of Moore’s Law
Wednesday, March 9, 2016 - 1:30pm to 2:45pm
Skilling Auditorium
Greg Yeric (ARM)
Abstract / Description: 

Scaling down into nanometer sizes is no longer a straightforward exercise. Moore's Law scaling as we have known it is officially slowing down. And while Moore's Law grabs all the headlines, more importantly to circuit designers, Dennard scaling (power and performance) is also slowing down. This talk will examine transistor scaling options, and what they might mean to circuit design scaling. We'll also look at non-traditional scaling routes, beyond standard CMOS digital logic. We'll find that students today can expect an interesting landscape of possible technologies to work with.


Greg Yeric earned his BSEE, MSEE, and PhD in Microelectronics at The University of Texas at Austin, in 1987, 1989, and 1993, respectively. Dr. Yeric began his career at Motorola's Advanced Products Research and Development Laboratories in the area of semiconductor process integration, subsequently working at TestChip Technologies, HPL Technologies, and Synopsys, in the areas of test structures, technology development, and yield analysis. For the last 8 years, he has been with ARM Holdings in Austin, Texas, where he leads the Silicon Technology group at ARM Research. His group's activities include design-technology co-optimization, predictive technology, and novel technology incubation.