A simulation based technique for material characterization: Electrical defect spectroscopy for novel device engineering and performance/reliability prediction

Topic: 
A simulation based technique for material characterization: Electrical defect spectroscopy for novel device engineering and performance/reliability prediction
Thursday, October 12, 2017 - 4:15pm
Venue: 
Allen 338X
Speaker: 
Prof. Luca Larcher (University of Modena and Reggio Emilia, Reggio Emilia (Italy))
Abstract / Description: 

In this work we will present a simulation-based technique that allows an in depth characterization of microscopic material properties including defects (e.g. distribution within the bandgap, atomic properties), which are crucial to either engineer novel memory devices (e.g. DRAM, RRAM, FeRAM, ...) and predict electron device reliability and variability.

This technique is based on a multiscale modeling and simulation platform connecting microscopic material properties to device electrical characteristics, which relies on a novel material-related microscopic approach for the description of the physical mechanisms governing charge-transport and material changes occurring during the device operation and aging. Charge trapping and transport (dominated by defect-assisted contributions), are self-consistently modeled by accounting for power dissipation and temperature increase, and a variety of material changes such as bond breakage and restoration, redox, drift and diffusion of atomic species, phase changes including ferroelectricity.

Automatic tools for the multiscale simulations and interpretation of the electrical measurements (e.g. I-V, C-V, G-V, BTI) allows extracting the main material properties of device materials including atomic defects, which severely affect the electrical device behavior of a wide class of memory (DRAM, RRAM, BEOL selectors, FeRAM, PCM) and logic (MOSFET, FinFET) devices. Examples of the application of this electrical defect spectroscopy technique to some of the above cases will be shown, allowing a fast material characterization and the identification of the location in energy and space coordinates of defects mostly affecting the electrical device characteristics.

Once the defect landscape and its connection to technology and process, simulations can then be used to project the device scaling, variability and reliability, and to design novel devices such as ReRAMs, Selectors and Ferroelectric devices, which will be shown in the presentation.

Bio:

Luca Larcher received the Ph.D. degree in "Information Engineering" from the University of Modena and Reggio Emilia in 2002. He is currently a professor of Electronics at the University of Modena and Reggio Emilia.

His main research interests include the modeling and characterization of non-volatile memory devices and of physical mechanisms governing the charge transport and degradation in high-k dielectrics. In this area, he has worked on either classical Flash memory devices and innovative NVM technologies such as charge trapping memory devices (NROM, SONOS, TANOS), PCM and RRAM devices. In 2013 he co-founded a start-up company developing novel software solution for the simulation of emerging electron devices such as RRAM. He is also active in the characterization and design of integrated circuits for both communications and energy harvesting applications in CMOS technology.

He authored and co-authored a book and a chapter in a book, and more than 200 technical papers published on international journals and proceedings of international conferences. He has joined the technical and executive committees of the IEDM, IRPS, ESREF, DATE, IIRW.

Andrea Padovani received the Ph.D. degree in 2010 from the University of Ferrara, Italy. He has been a fixed-term Assistant Professor and Adjunct Professor at the University of Modena and Reggio Emilia, Italy. He is a co-founder of MDLSoft Inc., a Silicon Valley company developing and marketing software solutions for the simulation of micro/nano-electronic devices. He is currently the VP for Customer Relationship Management and Lead Application Engineer of the company.

His research interests include the modeling of dielectric degradation and breakdown of high-k/metal gate transistors and the modeling of innovative nonvolatile memories and devices. He authored and coauthored more than 120 technical papers.