Recent years have seen an explosive growth in bandwidth requirements at all levels of computing, from consumer-grade GPUs to datacenters and supercomputers. Consensus is growing that traditional interconnect development is reaching its limits. Electrical I/O is limited to line data rates of around 112 Gbps, given physical limits of copper and dielectrics losses, and noise. Proposed approaches to surpass this limit increasingly offer higher rates without providing any real benefit; bandwidth comes with degradation of power consumption, complexity, and cost. Furthermore, the 112 Gbps limit is achievable only over very short distances, constraining the architecture of computer systems.
Photonic I/O is the only viable, near-term path to increasing data rates, and to solving the problems of power consumption, bandwidth, and latency faced by electrical I/O. Its low latency and low propagation loss can enable new "disaggregated" computer architectures, with separate chips of memory and logic linked over larger distances for more efficient utilization.
Ayar labs is pursuing a photonic interconnect solution that involves an external multi-wavelength laser source, an integrated transceiver chip with photonics densely integrated along with CMOS circuits, along with advanced chip packaging and optical-fiber connectivity. The transceiver chip integrates electro-optic modulators and detectors with analog drivers, control logic, and SERDES, taking advantage of dense integration to reduce parasitics, power consumption, latency, and packaging costs. Micro-rings provide wavelength-division multiplexing of many channels needed to achieve high capacity per chip edge at low power consumption. This development comes at an exciting time: the emergence of a large-scale process for CMOS-compatible photonics along with and advanced packaging ecosystem is converging with an acute market need for bandwidth density.