Neuromorphic computing is a promising concept for low-power, energy-efficient spiking networks with the capability of self-learning, adaptation, and recognition of speech, gesture, and objects. Development of the neuromorphic computing technology is currently facing 2 main barriers: First, there is no comprehensive understanding how the brain really works; and second, there is no consensus about what technology might provide synaptic and neural circuits at the best tradeoff between cost, power consumption, and performance. The resistive switching memory (RRAM) is one of the main contender for neuromorphic components, thanks to its low current operation, small area and tunable resistance. Demonstration of brain-inspired learning feature with RRAM synapses may pave the way for future high performance, low cost neuromorphic processor and brain-in-a-chip.
This talk will report on the recent advances on neuromorphic hardware for unsupervised learning of visual patterns. First, I will describe a RRAM synapse capable of spike-timing dependent plasticity (STDP) with one-transistor/one-resistor (1T1R) structure. Second, I will show the learning and recognition capability of a neuromorphic chip with a microcontroller neuron and an array of RRAM synapses. Learning of single/multiple patterns, tracking of patterns, and recognition will be shown in hardware. These results support RRAM as a promising technology for future neuromorphic processors.
Daniele Ielmini is a Professor at the Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Italy. After receiving his Ph.D. in Nuclear Engineering from Politecnico di Milano in 2000, he joined DEIB in 2002. He held visiting positions at Intel Corporation (2006), Stanford University (2006) and the University of Illinois at Urbana-Champaign (2010). His research interests include the modeling and characterization of non-volatile memories, such as nanocrystal memory, charge trap memory, phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM). He authored/coauthored 9 book chapters, more than 250 papers published in international journals and presented at international conferences, and 6 patents. He is Associate Editor of IEEE Trans. Nanotechnology and Semiconductor Science and Technology (IOP), and a Senior Member of the IEEE. He was recognized a Highly Cited Researcher by Thomson Reuters in 2015. He received the Intel Outstanding Researcher Award in 2013, the ERC Consolidator Grant in 2014, and the IEEE-EDS Paul Rappaport Award in 2015.