Nanoscale cascaded plasmonic logic gates for non-boolean wave computation

Topic: 
Nanoscale cascaded plasmonic logic gates for non-boolean wave computation
Monday, October 29, 2018 - 3:00pm
Venue: 
Gates 304
Speaker: 
Dr. Francky Catthoor (Inter-University Micro-Electronics Center (IMEC))
Abstract / Description: 

Several Beyond CMOS options for logic computing have been explored in the last decade. It is clear that beating ''ultimate CMOS'' is extremely hard when viewed at the functional level, where an algorithm with loops, control and arithmetic operations has to be executed in a given amount of time. Both the total area and total energy should be very reduced to improve beyond ultimate scaled CMOS. In this talk, wave based computing based on plasmonics technology will be discussed and evaluated. Based on some of the characteristics it may have some clear potential, though many challenges remain.

Bio:

Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. Between 1987 and 2000, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies. Since 2000 he is also strongly involved in other activities at IMEC including related application and deep submicron technology aspects, biomedical imaging and sensor nodes, and smart photo-voltaic modules, all at the Inter-university Micro-Electronics Center (IMEC), Heverlee, Belgium. Currently he is an IMEC fellow. He is part-time full professor at the EE department of the K.U.Leuven.

In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council.

He has been associate editor for several IEEE and ACM journals, like Trans. on VLSI Signal Processing, Trans. on Multi-media, and ACM TODAES.
He has been elected an IEEE fellow in 2005.