Emerging nanomaterials, such as carbon nanotubes (CNTs), have great potential to revolutionize future electronic systems. For instance, carbon nanotube field-effect transistors (CNFETs) are projected to improve the energy efficiency of digital systems by an order of magnitude compared to silicon CMOS. Unfortunately, CNTs face major obstacles such as substantial imperfections and variations inherent to CNTs, and low CNFET current densities. These obstacles limited CNFET demonstrations to stand-alone transistors or logic gates, with severely limited performance, yield, and scalability. In this talk, I will describe how to overcome these challenges through a combination of new CNT processing and CNFET circuit design solutions. This new approach transforms CNTs from solely a scientifically-interesting material to working nanosystems such as the first microprocessor [Nature 2013] and the first digital sub- systems [ISSCC 2013, JSSC 2014, ACS Nano 2014] built entirely using CNFETs. These are the first system-level demonstrations among promising emerging nanotechnologies for high- performance and highly energy-efficient digital systems. I will also demonstrate the highest current-drive CNFETs to-date, which are, for the first time, competitive with comparably-sized silicon-based transistors available from commercial foundries [IEDM 2014].
I will also discuss how CNTs are naturally suited for enabling new system architectures, such as monolithically-integrated three-dimensional (3D) integrated circuits. Monolithic 3D integration allows for computation immersed in memory by creating massive connectivity between vertically-interleaved layers of logic and memory. Such architectures are key to achieving high degrees of energy efficiency for emerging abundant-data applications. I will demonstrate the first monolithically-integrated 3D nanosystems combining arbitrary vertical- interleaving layers of emerging memories (Resistive RAM) and CNFET-based digital logic, fabricated directly over a silicon CMOS substrate [VLSI Tech. 2014, IEDM 2014].
Max Shulaker is a PhD candidate in Electrical Engineering at Stanford University, under the supervision of Professor Subhasish Mitra and co-advised by Professor Philip Wong. He received his B.S. from Stanford University in Electrical Engineering. Max's current research interests are in the broad area of nanosystems. His research results include the demonstration of the first carbon nanotube computer (highlighted on the cover of Nature, Sept. 2013), the first digital sub-systems built entirely using carbon nanotube FETs (awarded the ISSCC Jack Raper Award for Outstanding Technology-Directions Paper, 2013), the first monolithically-integrated 3D integrated circuits combining arbitrary vertical stacking of logic and memory (IEDM 2014), and the highest-performance CNFETs to-date (IEDM 2014). Max also enjoys teaching and has been a guest lecturer in several classes at Stanford. He is a Fannie and John Hertz Fellow and a Stanford Graduate Fellow.