EE Special Seminar

Power / Performance Optimization for High-End Microprocessors
Thursday, April 30, 2015 - 4:00pm to 5:30pm
Gates 415
David J. O'Brien
Abstract / Description: 

A Classic ATE testing focuses on finding defective units and, eliminating them. This talk is about the good units that are left – Bin Split 101. There will be a discussion of manufacturing flow, distributions, and optimizations using testing.


David J. O'Brien is an Intel Fellow in the Platform Engineering Group and the chief technologist for the Manufacturing Development Organization at Intel Corporation. He is responsible for silicon manufacturing development and system usage optimizations, and for fostering new business opportunities for Intel through product manufacturing systems and product definition.

Since joining Intel in 1989, O'Brien has been a product development engineer dedicated to silicon manufacturing development that melds architecture, design, validation and reliability. His Intel career began with the 80960 family of microcontrollers, followed by multiprocessor system cache memory and the Intel® Pentium® Pro processor. He later turned his attention to the first and subsequent generations of the Pentium 4 family of processors. Most recently, O'Brien has focused his technical capabilities on the first and fourth generations of Intel® Core™ processors. A principal engineer since 2000, he has accrued extensive expertise in product bin splits, platform implications and product testing in high-volume manufacturing.

O'Brien holds six patents in the field of semiconductor testing and is frequently invited to speak at industry events on the topic of semiconductor manufacturing and testing. At Intel, his contributions have been honored three times — in 2003, 2004 and 2014 — with Intel Achievement Awards, the company's highest technical award.

O'Brien holds a bachelor's degree in electrical engineering from Arizona State University and is a member of the Institute of Electrical and Electronics Engineers.