EE Special Seminar

Aging characterization of scaled Metal Gate / High-K devices and its impact on CMOS circuit degradation
Friday, April 24, 2015 - 3:00pm to 4:00pm
Gates 104
Abstract / Description: 

Time-zero variability and variability induced by device aging is a growing concern for aggressively scaled transistor technologies with metal gate/high-k stacks. Bias temperature instability (BTI) in PMOS and NMOS devices is considered the most dominant time-dependent variability contributor and needs to be modeled using stochastic processes. The physical nature of the stochastic process is still under debate and to support model development efforts large statistical data sets are essential. In this presentation, we will focus on the characterization challenges related to the BTI process in large and small area CMOS devices and discuss how to obtain discrete SRAM and logic device level data beyond 3s. We will further illustrate the impact of the stochastic variation on CMOS circuits like SRAM and ring-oscillators. Finally we will highlight opportunities for application of time-resolved electrical characterization methods to improve the understanding of novel devices.


Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2014. From 1999 – 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. In 2006, he joined AMD in Yorktown Heights, NY, and now is with GLOBALFOUNDRIES in Malta, NY, working as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. Dr. Kerber has contributed to more than 95 journal and conference publications and presented his work at international conferences, including the VLSI, IEDM and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW and IRPS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IEDM, Infos and is a Senior Member of the IEEE.