We developed 3D stacked 16 million pixel CMOS image sensor to achieve ideal image sensor and Global shutter performance, using 4 million micro bump inter-connections at a 7.6-um pitch with wafer bonding technology. We then evaluated its reliability. This 3D stacked technology was proven to have no negative effect on CIS characteristics and to provide a high density and narrow pitched in-pixel connection with high reliability, no defects, and no deterioration over a 1000-cycle heat cycle test and after a 1000-hour high temperature and high humidity test. This CIS sensor has a set of readout circuits in each substrate, which enable us to detect any connection failure among 4 million micro bumps between substrates individually. These results show that this 3D technology has enough reliability for application to products like multi band imaging.
Yoshiaki Takemoto received B.S. and M.S. degrees in electrical engineering from Osaka University, Osaka, Japan. In 2010, he joined the Corporate R&D Center, Olympus Corporation, Tokyo, Japan, where he has been working on the research and development of CMOS image sensors. He is currently engaged in research of the fabrication process and design in 3D stacking technology.
Yoshitaka Tadaki (M'90) received B.S., M.S., and Ph.D. degrees from Tohoku University, Sendai, Japan. In 1982, he joined the Device Development Center, Hitachi, Ltd., Tokyo, Japan, where he was engaged in the development of process integration and device structure for DRAMs. From 1989 to 1990, he was a visiting scholar at Stanford University, Stanford, CA, USA. In 2008, he joined the Corporate R&D Center, Olympus Corporation, Tokyo, Japan, where he has been working on the research and development of CMOS image sensors. He is the holder of 104 Japanese patent applications.