The capacity and bandwidth of DRAM, a de-facto standard main memory for decades, have steadily improved over time by taking advantage of Moore's law. In addition to the capacity and bandwidth scaling, more attention has been drawn recently to other important aspects of memory, such as latency, energy efficiency, and reliability, on main memory DRAM research and development. In this talk, I will summarize my research efforts on improving various aspects of main memory DRAM, such as 1) reducing access latency with asymmetric DRAM bank organization and row-buffer decoupling, 2) improving energy efficiency with a judicious use of silicon interposer and micro-banks, and 3) retaining die yield with low area overhead through DRAM-side caching. In contrast to these studies that require hardware changes and rely on simulators for evaluation, recently I have also been focusing on memory system performance enhancement of existing servers, such as reducing inter-thread interference to memory channels through address remapping/staggering, scatter-gather without bandwidth waste, and selective caching.
Jung Ho Ahn is an associate professor at Seoul National University. Professor Ahn received his PhD in electrical engineering from Stanford University, was a senior research scientist at HP labs before joining Seoul National University, and took sabbatical at Google recently. His research interests include bridging the gap between the performance demand of emerging applications and the performance potential or modern and future massively parallel systems, more specifically on memory subsystems.