At the 22nm technology node, 3-D or tri-gate transistors were introduced into high volume manufacturing. The introduction of a fully depleted 3-D transistor enables a reduction in power while reducing gate lengths for higher density. This talk will discuss the device physics of fully depleted transistors and the trade-offs of different fully-depleted architectures and why a 3-D structure was chosen. Use of a 3-D transistor posed several process challenges which needed to be overcome in introducing this structure to high volume manufacturing.
Chris Auth is a vice president at Intel Corporation and the director of advanced transistor development for the company’s Technology and Manufacturing Group. He is responsible for leading the development of Intel’s 10-nanometer (10nm) high-performance CMOS logic transistor process.
Auth joined Intel in 1997 in Santa Clara, Calif., as a senior process engineer for Flash memory process integration. From 1997 to 2000, he led the team developing the NOR Flash memory cell for the 180nm Flash process. In 2000, he joined the Logic Technology Development organization and led the team responsible for introducing the industry’s first use of strained silicon for transistor enhancement into the 90nm and 65nm CMOS flows. From 2005 to 2008, he led the process development and introduction of the industry-first, high-k/metal-gate process for the 45nm CMOS flow. Before assuming his current role, Auth led the process development and introduction of the industry-first, tri-gate process into the 22nm CMOS flow.
He holds seven patents in semiconductor devices and manufacturing and has received five Intel Achievement Awards for his role in developing leading-edge process technologies. He and his colleagues were also honored with a SEMI Award for North America, which recognized that the techniques pioneered by the team were widely adopted across the semiconductor industry.
Auth received his bachelor’s degree in electrical engineering from the University of Washington and earned his master’s and doctoral degrees in electrical engineering from Stanford University.