Publication # 311

A semiconductor processing method for the formation of self-aligned via and trench structures in III-V semiconductor devices (in particular, on InP platform) is presented, together with fabrication results. As a template for such self-aligned via and trench formations in a surrounding polymer layer on a semiconductor device, we make use of a sacrificial layer that consists of either a SiO2 dielectric hard mask layer deposited on the device layers or a sacrificial semiconductor layer grown on top of the device epitaxial layers (e.g., InP on an InGaAs etch stop), both laid down on the device layers before patterning the device geometry. During the semiconductor device etching, the sacrificial layer is kept as a part of the patterned structures and is, therefore, perfectly self-aligned. By selectively removing the sacrificial layer surrounded by the polymer that is etched back within the thickness of the sacrificial layer, an opening such as a via and a trench is formed perfectly self-aligned on the device top area in the place of the sacrificial layer. This process yields a pristine semiconductor surface for metal contacts and fully utilizes the contact area available on the device top, no matter how small the device area is. This approach thus provides as low an Ohmic contact resistance as. possible upon filling the via and the trench with metal deposition. The additional use of a thin Si3N4 protecting layer surrounding the device sidewalls improves the robustness of the process without any undesired impact on the device electrical passivation (or on the optical mode characteristics if the device also includes a waveguide). This method offers metal contacts scalable to the device size, being limited only by the feasible device size itself. This method is also applicable to the fabrication of other III-V based integrated devices.

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