Energy or Power minimization is a universal macro-constraint for on-chip architectures. The computer industry is actively dealing with trade-offs between performance and energy efficiency. Currently, the traditional way of scaling as per Moore's law reduces the critical dimensions of device with every generation of the technology. However, as the energy or power per switching operation is not scaling down the size, a newer technology does not directly translate to substantial advantage to our products. In addition, based on our estimates, the energy per operation (active power) is still about 104 higher than the thermodynamic limit of a binary switch.
The intent of this work is to develop theoretical concepts for bridging architectures with energy efficient computing. We evaluate the efficiency of an ideal computing architecture at the limits of scaling. We achieve this by using concepts from thermodynamics, classical mechanics, and quantum mechanics for simplified computing systems. Although efforts have been undertaken on scalability of single devices, we believe that this is the first attempt to estimate energy in large computing systems and in a single switch using the same physical principles. Similar to design of heat engines, we hope that these concepts will help in evaluating different chip architectures and compare them to a limiting and ideal computing engine. As a larger conclusion, we will also explore possibilities of reversible computing from this perspective and contrast it with Landauer- based estimate of switching energy.