50 Years in the Making: The Open RISC-V Instruction Set architecture [EE380 Computer Systems Colloquium & EE180]

50 Years in the Making: The Open RISC-V Instruction Set architecture
Thursday, March 16, 2017 -
10:30am to 11:30am
Cubberly Auditorium, School of Education
David Patterson (Google) and John Hennessy (Knight-Hennessy Scholars Program)
Abstract / Description: 

About the talk (10:30-11:30):
We start by reviewing 50 years of computer architecture to show there is now widespread agreement on instruction set architecture (ISA). Unlike other fields, despite this harmony there is no open alternative to proprietary offerings from ARM and Intel. Our champion is RISC-V, whose foundation has been joined by nearly every hi-tech company (except for the two with popular proprietary ISAs). We continue the discussion by focusing on the challenges ahead as IC technology slows down, older architectural approaches face diminishing returns, and the needs of users change dramatically.


General Information: This presentation is the last lecture of EE180 for Winter 2017. The lecture is open to the public. The lecture will not be video recorded nor available on the web.

EE380 students and attendees are urged to attend this lecture, but it is optional. It cannot be substituted for one of the ten required EE380 lectures.


Patterson's Bio:

After 40 years as a UC Berkeley professor, David Patterson retired in 2016 and joined Google as a distinguished engineer. He has been Chair of Berkeley's CS Division, Chair of the Computing Research Association, and President of the Association for Computing Machinery. His most successful research projects have been Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations. All helped lead to multibillion-dollar industries. This research led to many papers, six books, and about 40 honors, including election to the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and Fellow of the Computer History Museum. He shared the IEEE von Neumann Medal and the NEC C&C Prize with John Hennessy, past president of Stanford University and co-author of two of his books.

Hennessy Bio: 

John Hennessy initiated the MIPS project at Stanford in 1981, MIPS is a high-performance Reduced Instruction Set Computer (RISC), built in VLSI. MIPS was one of the first three experimental RISC architectures. In addition to his role in the basic research, Hennessy played a key role in transferring this technology to industry. During a sabbatical leave from Stanford in 1984-85, he cofounded MIPS Computer Systems (later MIPS Technologies Inc. and now part of Imagination Technologies), which specializes in the production of chips based on these concepts. He also led the Stanford DASH (Distributed Architecture for Shared Memory) multiprocessor project. DASH was the first scalable shared memory multiprocessor with hardware-supported cache coherence. More recently, he has been involved in FLASH (FLexible Architecture for Shared Memory), which is designed to support different communication and coherency approaches in large-scale shared-memory multiprocessors. In the 1990s, he served as the Founding Chairman of the Board of Atheros, an early wireless chipset company, now part of Qualcomm. Hennessy is also the coauthor of two widely used textbooks in computer architecture. In addition to his work as a Professor at Stanford, he has served as Chair of the Department of Computer Science (1994-96), Dean of the School of Engineering (1996-99), Provost (1999-2000), and President (2000-2016). He is currently the Director of the Knight-Hennessy Scholars Program, which each year will select 100 new graduate scholars from around the world to receive a full scholarship (with stipend) to pursue a wide-ranging graduate education at Stanford, with the goal of developing a new generation of global leaders.